Gopesh Bhardwaj
233 línte
9.8 KiB
C++
233 línte
9.8 KiB
C++
// MIT License
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//
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// Copyright (c) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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#include "agent.hpp"
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#include <cstring>
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#define CHECK_HSA(x) if ((x) != HSA_STATUS_SUCCESS) { std::cerr << __FILE__ << " error at " << __LINE__ << std::endl; exit(-1); }
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std::vector<std::shared_ptr<AgentInfo>> AgentInfo::gpu_agents{};
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hsa_agent_t AgentInfo::cpu_agent{0};
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hsa_amd_memory_pool_t AgentInfo::cpu_pool;
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hsa_amd_memory_pool_t AgentInfo::kernarg_pool;
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void AgentInfo::add_event(aqlprofile_pmc_event_t block, const std::string& counter, int block_cnt, int event_id)
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{
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block.event_id = event_id;
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std::vector<aqlprofile_pmc_event_t> cnt{};
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for (int i=0; i<block_cnt; i++)
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{
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block.block_index = i;
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cnt.push_back(block);
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}
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counters[counter] = std::move(cnt);
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}
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hsa_status_t AgentInfo::get_agent_handle_cb(hsa_agent_t agent, void* userdata)
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{
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hsa_device_type_t type;
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CHECK_HSA(hsa_agent_get_info(agent, HSA_AGENT_INFO_DEVICE, &type));
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if (type == HSA_DEVICE_TYPE_CPU)
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{
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cpu_agent = agent;
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return HSA_STATUS_SUCCESS;
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}
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std::shared_ptr<AgentInfo> info = std::make_shared<AgentInfo>();
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info->hsa_agent = agent;
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CHECK_HSA(hsa_agent_get_info(agent, HSA_AGENT_INFO_NAME, info->gfxip.data()));
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CHECK_HSA(hsa_agent_get_info(agent, static_cast<hsa_agent_info_t>(HSA_AMD_AGENT_INFO_NUM_XCC), &info->info.xcc_num));
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CHECK_HSA(hsa_agent_get_info(agent, static_cast<hsa_agent_info_t>(HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES), &info->info.se_num));
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CHECK_HSA(hsa_agent_get_info(agent, static_cast<hsa_agent_info_t>(HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT), &info->info.cu_num));
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CHECK_HSA(hsa_agent_get_info(agent, static_cast<hsa_agent_info_t>(HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE), &info->info.shader_arrays_per_se));
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info->info.agent_gfxip = info->gfxip.data();
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CHECK_HSA(aqlprofile_register_agent(&info->handle, &info->info));
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aqlprofile_pmc_event_flags_t flags{.raw = 0};
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aqlprofile_pmc_event_t grbm {.block_index = 0, .flags = flags, .block_name = HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM};
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aqlprofile_pmc_event_t sq {.block_index = 0, .flags = flags, .block_name = HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ};
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aqlprofile_pmc_event_t ta {.block_index = 0, .flags = flags, .block_name = HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA};
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aqlprofile_pmc_event_t tcp {.block_index = 0, .flags = flags, .block_name = HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP};
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aqlprofile_pmc_event_t tcc {.block_index = 0, .flags = flags, .block_name = HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC};
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aqlprofile_pmc_event_t gl2c {.block_index = 0, .flags = flags, .block_name = HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C};
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info->add_event(grbm, "GRBM_COUNT", 1, 0);
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info->add_event(grbm, "GRBM_GUI_ACTIVE", 1, 2);
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info->add_event(sq, "SQ_WAVES", 1, 4);
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info->add_event(sq, "SQ_BUSY_CYCLES", 1, 3);
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info->add_event(sq, "SQ_INSTS_VALU", 1, (info->gfxip.find("gfx1")==0) ? 62 : 26);
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info->add_event(ta, "TA_BUSY", 16, (info->gfxip.find("gfx94") != 0 || info->gfxip.find("gfx95") != 0) ? 13 : 15);
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if (info->gfxip.find("gfx1") == 0)
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{
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info->add_event(gl2c, "GL2C_REQ", 32, 3);
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info->add_event(gl2c, "GL2C_READ", 32, 6);
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info->add_event(gl2c, "GL2C_WRITE", 32, 7);
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}
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else if (info->gfxip.find("gfx95") == 0)
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{
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info->add_event(sq, "SQ_INSTS_VALU_FLOPS_FP32", 10, 82);
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info->add_event(sq, "SQ_INSTS_VALU_FLOPS_FP64", 10, 83);
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info->add_event(sq, "SQ_INSTS_VALU_FLOPS_FP32_TRANS", 10, 85);
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info->add_event(sq, "SQ_INSTS_VALU_FLOPS_FP64_TRANS", 10, 86);
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info->add_event(tcp, "TCP_READ", 10, 28);
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info->add_event(tcp, "TCP_WRITE", 10, 30);
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info->add_event(tcp, "TCP_CACHE_ACCESS", 10, 58);
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info->add_event(tcp, "TCP_CACHE_MISS_TG0", 10, 59);
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info->add_event(tcp, "TCP_CACHE_MISS_TG1", 10, 60);
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info->add_event(tcp, "TCP_CACHE_MISS_TG2", 10, 61);
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info->add_event(tcp, "TCP_CACHE_MISS_TG3", 10, 62);
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info->add_event(tcp, "TCP_CACHE_MISS", 10, 63);
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info->add_event(tcc, "TCC_EA0_RDREQ", 16, 42);
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info->add_event(tcc, "TCC_EA0_RDREQ_DRAM", 16, 108);
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info->add_event(tcc, "TCC_EA0_WRREQ_DRAM", 16, 109);
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info->add_event(tcc, "TCC_EA0_WRREQ_WRITE_DRAM", 16, 110);
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info->add_event(tcc, "TCC_EA0_WRREQ_ATOMIC_DRAM", 16, 111);
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info->add_event(tcc, "TCC_EA0_RDREQ_DRAM_32B", 16, 112);
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info->add_event(tcc, "TCC_EA0_RDREQ_GMI_32B", 16, 113);
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info->add_event(tcc, "TCC_EA0_RDREQ_IO_32B", 16, 114);
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info->add_event(tcc, "TCC_EA0_WRREQ_WRITE_DRAM_32B", 16, 115);
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info->add_event(tcc, "TCC_EA0_WRREQ_ATOMIC_DRAM_32B", 16, 116);
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info->add_event(tcc, "TCC_EA0_WRREQ_WRITE_GMI_32B", 16, 117);
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info->add_event(tcc, "TCC_EA0_WRREQ_ATOMIC_GMI_32B", 16, 118);
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info->add_event(tcc, "TCC_EA0_WRREQ_WRITE_IO_32B", 16, 119);
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info->add_event(tcc, "TCC_EA0_WRREQ_ATOMIC_IO_32B", 16, 119);
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}
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else if (info->gfxip.find("gfx94") == 0)
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{
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info->add_event(tcc, "TCC_REQ", 16, 3);
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info->add_event(tcc, "TCC_ATOMIC", 16, 14);
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info->add_event(tcc, "TCC_EA0_ATOMIC", 16, 36);
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info->add_event(tcc, "TCC_EA0_WRREQ_CREDIT_STALL", 16, 30);
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info->add_event(tcc, "TCC_EA0_WRREQ_IO_CREDIT_STALL", 16, 31);
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info->add_event(tcc, "TCC_EA0_WRREQ_GMI_CREDIT_STALL", 16, 32);
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info->add_event(tcc, "TCC_EA0_WRREQ_DRAM_CREDIT_STALL", 16, 33);
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info->add_event(tcc, "TCC_EA0_RDREQ", 16, 38);
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info->add_event(tcc, "TCC_EA0_RDREQ_IO_CREDIT_STALL", 16, 41);
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info->add_event(tcc, "TCC_EA0_RDREQ_GMI_CREDIT_STALL", 16, 42);
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info->add_event(tcc, "TCC_EA0_RDREQ_DRAM_CREDIT_STALL", 16, 43);
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info->add_event(tcp, "TCP_READ", 10, 28);
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info->add_event(tcp, "TCP_WRITE", 10, 30);
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info->add_event(tcp, "TCP_CACHE_ACCESS", 10, 60);
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info->add_event(tcp, "TCP_CACHE_MISS_TG0", 10, 61);
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info->add_event(tcp, "TCP_CACHE_MISS_TG1", 10, 62);
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info->add_event(tcp, "TCP_CACHE_MISS_TG2", 10, 63);
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info->add_event(tcp, "TCP_CACHE_MISS_TG3", 10, 64);
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}
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else if (info->gfxip.find("gfx90a") == 0)
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{
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info->add_event(tcp, "TCP_READ", 16, 30);
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info->add_event(tcp, "TCP_WRITE", 16, 32);
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}
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else if (info->gfxip.find("gfx900") == 0)
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{
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info->add_event(tcp, "TCP_READ", 16, 30);
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info->add_event(tcp, "TCP_WRITE", 16, 32);
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}
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else
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{
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assert(false);
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}
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gpu_agents.push_back(info);
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return HSA_STATUS_SUCCESS;
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}
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hsa_status_t
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FindGlobalPool(hsa_amd_memory_pool_t pool, void* data)
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{
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hsa_amd_segment_t segment;
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CHECK_HSA(hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SEGMENT, &segment));
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if(HSA_AMD_SEGMENT_GLOBAL != segment) return HSA_STATUS_SUCCESS;
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uint32_t flag;
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CHECK_HSA(hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS, &flag));
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uint32_t karg_st = flag & HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT;
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if (karg_st)
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AgentInfo::kernarg_pool = pool;
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else
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AgentInfo::cpu_pool = pool;
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return HSA_STATUS_SUCCESS;
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}
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void AgentInfo::iterate_agents()
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{
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CHECK_HSA(hsa_iterate_agents(get_agent_handle_cb, nullptr));
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CHECK_HSA(hsa_amd_agent_iterate_memory_pools(cpu_agent, FindGlobalPool, nullptr));
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}
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bool
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Queue::Submit(hsa_ext_amd_aql_pm4_packet_t* packet)
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{
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const uint64_t write_idx = hsa_queue_add_write_index_relaxed(queue, 1);
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size_t index = (write_idx % queue->size) * sizeof(hsa_ext_amd_aql_pm4_packet_t);
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auto* queue_slot = reinterpret_cast<uint32_t*>(size_t(queue->base_address) + index); // NOLINT
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const auto* slot_data = reinterpret_cast<const uint32_t*>(packet);
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std::memcpy(&queue_slot[1], &slot_data[1], sizeof(hsa_ext_amd_aql_pm4_packet_t) - sizeof(uint32_t));
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auto* header = reinterpret_cast<std::atomic<uint32_t>*>(queue_slot);
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header->store(slot_data[0], std::memory_order_release);
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hsa_signal_store_screlease(queue->doorbell_signal, write_idx);
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int loops = 0;
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while(hsa_queue_load_read_index_relaxed(queue) <= write_idx)
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{
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loops++;
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usleep(1);
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if(loops > 10000)
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{
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std::cerr << "Codeobj packet submission failed!" << std::endl;
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return false;
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}
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}
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return true;
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}
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Queue::Queue(std::shared_ptr<AgentInfo>& _agent): agent(_agent)
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{
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CHECK_HSA(hsa_queue_create(agent->hsa_agent, 64, HSA_QUEUE_TYPE_SINGLE, NULL, NULL, UINT32_MAX, UINT32_MAX, &this->queue));
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}
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void Queue::flush()
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{
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return;
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hsa_barrier_and_packet_t barrier{};
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barrier.header = HSA_PACKET_TYPE_BARRIER_OR | (1<<HSA_PACKET_HEADER_BARRIER);
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barrier.header |= HSA_FENCE_SCOPE_SYSTEM<<HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE;
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barrier.header |= HSA_FENCE_SCOPE_SYSTEM<<HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE;
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Submit((hsa_ext_amd_aql_pm4_packet_t*)&barrier);
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} |