Sylvain Jeaugey
40adc74496
Add support for network collectives.
Add support for XML topology dump/injection.
Add text values for GDR and P2P Levels, including "NVL".
Add speed detection for PCI, Infiniband and Ethernet cards.
Add CPU detection for ARM and AMD CPUs.
Add support for adaptive routing on Infiniband.
Change NET plugin API to v3 : merge PCI path and GPU pointer
capability into a single structure and add other properties.
[ROCm/rccl commit: b221128eca]
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/*************************************************************************
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* See LICENSE.txt for license information
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************************************************************************/
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#ifndef NCCL_CPUSET_H_
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#define NCCL_CPUSET_H_
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// Convert local_cpus, e.g. 0003ff,f0003fff to cpu_set_t
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static int hexToInt(char c) {
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int v = c - '0';
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if (v < 0) return -1;
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if (v > 9) v = 10 + c - 'a';
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if ((v < 0) || (v > 15)) return -1;
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return v;
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}
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#define CPU_SET_N_U32 (sizeof(cpu_set_t)/sizeof(uint32_t))
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ncclResult_t ncclStrToCpuset(const char* str, cpu_set_t* mask) {
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uint32_t cpumasks[CPU_SET_N_U32];
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int m = CPU_SET_N_U32-1;
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cpumasks[m] = 0;
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for (int o=0; o<strlen(str); o++) {
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char c = str[o];
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if (c == ',') {
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m--;
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cpumasks[m] = 0;
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} else {
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int v = hexToInt(c);
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if (v == -1) break;
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cpumasks[m] <<= 4;
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cpumasks[m] += v;
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}
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}
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// Copy cpumasks to mask
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for (int a=0; m<CPU_SET_N_U32; a++,m++) {
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memcpy(((uint32_t*)mask)+a, cpumasks+m, sizeof(uint32_t));
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}
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return ncclSuccess;
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}
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ncclResult_t ncclCpusetToStr(cpu_set_t* mask, char* str) {
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int c = 0;
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uint8_t* m8 = (uint8_t*)mask;
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for (int o=sizeof(cpu_set_t)-1; o>=0; o--) {
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if (c == 0 && m8[o] == 0) continue;
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sprintf(str+c, "%02x", m8[o]);
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c+=2;
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if (o && o%4 == 0) {
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sprintf(str+c, ",");
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c++;
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}
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}
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str[c] = '\0';
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return ncclSuccess;
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}
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#endif
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