Vladislav Sytchenko
99e8ac55cd
Since the majority of the Hostcall implementation now sits in the commmon layer, the PAL backend simply just needs to invoke it. One thing that is missing though is HSA signal support. The newly added pal::Signal class is a light emulaion of what HSA signals provide. The current implementation is just enough to get Hostcall working, but it can be expanded in the future if needed to fully emulate HSA signals. The major difference for now between PAL and ROCm hostcall implemenations is that PAL doesn't support blocking signals. This will be enabled in the near future. For now use active wait for PAL. Change-Id: I746557354ab9d71a7d4a31f9320fcc2fee5aee7f
752 lines
29 KiB
C++
752 lines
29 KiB
C++
/* Copyright (c) 2015-present Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#pragma once
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#include <queue>
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#include "device/pal/paldefs.hpp"
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#include "device/pal/palconstbuf.hpp"
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#include "device/pal/palprintf.hpp"
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#include "device/pal/paltimestamp.hpp"
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#include "device/pal/palsched.hpp"
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#include "device/pal/paldebugger.hpp"
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#include "device/pal/palgpuopen.hpp"
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#include "platform/commandqueue.hpp"
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#include "device/blit.hpp"
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#include "palUtil.h"
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#include "palCmdBuffer.h"
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#include "palCmdAllocator.h"
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#include "palQueue.h"
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#include "palFence.h"
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#include "palLinearAllocator.h"
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/*! \addtogroup PAL PAL Resource Implementation
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* @{
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*/
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//! PAL Device Implementation
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namespace pal {
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class Device;
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class Kernel;
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class Memory;
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class CalCounterReference;
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class VirtualGPU;
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class Program;
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class BlitManager;
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class ThreadTrace;
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class HSAILKernel;
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//! Virtual GPU
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class VirtualGPU : public device::VirtualDevice {
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public:
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class Queue : public amd::HeapObject {
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public:
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static constexpr uint MaxCommands = 256;
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static constexpr uint StartCmdBufIdx = 1;
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static constexpr uint FirstMemoryReference = 0x80000000;
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static constexpr uint64_t WaitTimeoutInNsec = 6000000000;
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static constexpr uint64_t PollIntervalInNsec = 200000;
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Queue(const Queue&) = delete;
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Queue& operator=(const Queue&) = delete;
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static Queue* Create(const VirtualGPU& gpu, //!< OCL virtual GPU object
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Pal::QueueType queueType, //!< PAL queue type
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uint engineIdx, //!< Select particular engine index
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Pal::ICmdAllocator* cmdAlloc, //!< PAL CMD buffer allocator
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uint rtCU, //!< The number of reserved CUs
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amd::CommandQueue::Priority priority, //!< Queue priority
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uint64_t residency_limit, //!< Enables residency limit
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uint max_command_buffers //!< Number of allocated command buffers
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);
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Queue(const VirtualGPU& gpu, Pal::IDevice* iDev, uint64_t residency_limit,
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uint max_command_buffers)
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: lock_(nullptr),
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iQueue_(nullptr),
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iCmdBuffs_(max_command_buffers, nullptr),
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iCmdFences_(max_command_buffers, nullptr),
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last_kernel_(nullptr),
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gpu_(gpu),
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iDev_(iDev),
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cmdBufIdSlot_(StartCmdBufIdx),
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cmdBufIdCurrent_(StartCmdBufIdx),
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cmbBufIdRetired_(0),
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cmdCnt_(0),
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vlAlloc_(64 * Ki),
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residency_size_(0),
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residency_limit_(residency_limit),
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max_command_buffers_(max_command_buffers) {
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vlAlloc_.Init();
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}
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~Queue();
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void addCmdMemRef(GpuMemoryReference* mem);
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void removeCmdMemRef(GpuMemoryReference* mem);
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void addCmdDoppRef(Pal::IGpuMemory* iMem, bool lastDoppCmd, bool pfpaDoppCmd);
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void addMemRef(Pal::IGpuMemory* iMem) const {
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Pal::GpuMemoryRef memRef = {};
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memRef.pGpuMemory = iMem;
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iDev_->AddGpuMemoryReferences(1, &memRef, nullptr, Pal::GpuMemoryRefCantTrim);
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}
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void removeMemRef(Pal::IGpuMemory* iMem) const {
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iDev_->RemoveGpuMemoryReferences(1, &iMem, nullptr);
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}
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// Notice KMD to update applicaiton profile
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Pal::Result UpdateAppPowerProfile();
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// ibReuse forces event wait without polling, to make sure event occured
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template <bool ibReuse> bool waifForFence(uint cbId) const {
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Pal::Result result = Pal::Result::Success;
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uint64_t start;
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uint64_t end;
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if (!ibReuse) {
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start = amd::Os::timeNanos();
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}
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while ((Pal::Result::Success != (result = iCmdFences_[cbId]->GetStatus())) || ibReuse) {
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if (result == Pal::Result::ErrorFenceNeverSubmitted) {
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result = Pal::Result::Success;
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break;
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}
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if (!ibReuse) {
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end = amd::Os::timeNanos();
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}
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if (!ibReuse && ((end - start) < PollIntervalInNsec)) {
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amd::Os::yield();
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continue;
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}
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result = iDev_->WaitForFences(1, &iCmdFences_[cbId], true, WaitTimeoutInNsec);
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if (Pal::Result::Success == result) {
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break;
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} else if ((Pal::Result::NotReady == result) || (Pal::Result::Timeout == result)) {
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LogWarning("PAL fence isn't ready!");
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if (GPU_ANALYZE_HANG) {
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DumpMemoryReferences();
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}
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} else {
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LogError("PAL wait for a fence failed!");
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break;
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}
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}
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return (result == Pal::Result::Success) ? true : false;
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}
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//! Flushes the current command buffer to HW
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//! Returns ID associated with the submission
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template <bool avoidBarrierSubmit = false> uint submit(bool forceFlush);
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bool flush();
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bool waitForEvent(uint id);
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bool isDone(uint id);
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Pal::ICmdBuffer* iCmd() const { return iCmdBuffs_[cmdBufIdSlot_]; }
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uint cmdBufId() const { return cmdBufIdCurrent_; }
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static uint32_t AllocedQueues(const VirtualGPU& gpu, Pal::EngineType type);
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amd::Monitor* lock_; //!< Lock PAL queue for access
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Pal::IQueue* iQueue_; //!< PAL queue object
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std::vector<Pal::ICmdBuffer*> iCmdBuffs_; //!< PAL command buffers
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std::vector<Pal::IFence*> iCmdFences_; //!< PAL fences, associated with CMD
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const amd::Kernel* last_kernel_; //!< Last submitted kernel
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private:
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void DumpMemoryReferences() const;
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const VirtualGPU& gpu_; //!< OCL virtual GPU object
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Pal::IDevice* iDev_; //!< PAL device
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uint cmdBufIdSlot_; //!< Command buffer ID slot for submissions
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uint cmdBufIdCurrent_; //!< Current global command buffer ID
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uint cmbBufIdRetired_; //!< The last retired command buffer ID
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uint cmdCnt_; //!< Counter of commands
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std::unordered_map<GpuMemoryReference*, uint> memReferences_;
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Util::VirtualLinearAllocator vlAlloc_;
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std::vector<Pal::GpuMemoryRef> palMemRefs_;
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std::vector<Pal::IGpuMemory*> palMems_;
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std::vector<Pal::DoppRef> palDoppRefs_;
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std::set<Pal::IGpuMemory*> sdiReferences_;
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std::vector<const Pal::IGpuMemory*> palSdiRefs_;
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uint64_t residency_size_; //!< Resource residency size
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uint64_t residency_limit_; //!< Enables residency limit
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uint max_command_buffers_;
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};
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struct CommandBatch : public amd::HeapObject {
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amd::Command* head_; //!< Command batch head
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GpuEvent events_[AllEngines]; //!< Last known GPU events
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TimeStamp* lastTS_; //!< TS associated with command batch
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//! Constructor
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CommandBatch(amd::Command* head, //!< Command batch head
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const GpuEvent* events, //!< HW events on all engines
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TimeStamp* lastTS //!< Last TS in command batch
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) {
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init(head, events, lastTS);
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}
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void init(amd::Command* head, //!< Command batch head
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const GpuEvent* events, //!< HW events on all engines
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TimeStamp* lastTS //!< Last TS in command batch
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) {
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head_ = head;
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lastTS_ = lastTS;
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memcpy(&events_, events, AllEngines * sizeof(GpuEvent));
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}
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};
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//! The virtual GPU states
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union State {
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struct {
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uint profiling_ : 1; //!< Profiling is enabled
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uint forceWait_ : 1; //!< Forces wait in flush()
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uint profileEnabled_ : 1; //!< Profiling is enabled for WaveLimiter
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uint perfCounterEnabled_ : 1; //!< PerfCounter is enabled
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uint rgpCaptureEnabled_ : 1; //!< RGP capture is enabled in the runtime
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uint imageBufferWrtBack_ : 1; //!< Enable image buffer write back
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};
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uint value_;
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State() : value_(0) {}
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};
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typedef std::vector<ConstantBuffer*> constbufs_t;
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class MemoryDependency : public amd::EmbeddedObject {
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public:
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//! Default constructor
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MemoryDependency()
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: memObjectsInQueue_(nullptr), numMemObjectsInQueue_(0), maxMemObjectsInQueue_(0) {}
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~MemoryDependency() { delete[] memObjectsInQueue_; }
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//! Creates memory dependecy structure
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bool create(size_t numMemObj);
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//! Notify the tracker about new kernel
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void newKernel() { endMemObjectsInQueue_ = numMemObjectsInQueue_; }
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//! Validates memory object on dependency
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void validate(VirtualGPU& gpu, const Memory* memory, bool readOnly);
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//! Invalidates GPU caches if memory dependency tracking is disabled
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void sync(VirtualGPU& gpu) const {
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if (maxMemObjectsInQueue_ == 0) {
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gpu.addBarrier(RgpSqqtBarrierReason::MemDependency);
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}
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}
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//! Clear memory dependency
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void clear(bool all = true);
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private:
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struct MemoryState {
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uint64_t start_; //! Busy memory start address
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uint64_t end_; //! Busy memory end address
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bool readOnly_; //! Current GPU state in the queue
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};
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MemoryState* memObjectsInQueue_; //!< Memory object state in the queue
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size_t endMemObjectsInQueue_; //!< End of mem objects in the queue
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size_t numMemObjectsInQueue_; //!< Number of mem objects in the queue
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size_t maxMemObjectsInQueue_; //!< Maximum number of mem objects in the queue
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};
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class DmaFlushMgmt : public amd::EmbeddedObject {
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public:
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DmaFlushMgmt(const Device& dev);
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// Resets DMA command buffer workload
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void resetCbWorkload(const Device& dev);
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// Finds split size for the current dispatch
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void findSplitSize(const Device& dev, //!< GPU device object
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uint64_t threads, //!< Total number of execution threads
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uint instructions //!< Number of ALU instructions
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);
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// Returns TRUE if DMA command buffer is ready for a flush
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bool isCbReady(VirtualGPU& gpu, //!< Virtual GPU object
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uint64_t threads, //!< Total number of execution threads
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uint instructions //!< Number of ALU instructions
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);
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// Returns dispatch split size
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uint dispatchSplitSize() const { return dispatchSplitSize_; }
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private:
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uint64_t maxDispatchWorkload_; //!< Maximum number of operations for a single dispatch
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uint64_t maxCbWorkload_; //!< Maximum number of operations for DMA command buffer
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uint64_t cbWorkload_; //!< Current number of operations in DMA command buffer
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uint aluCnt_; //!< All ALUs on the chip
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uint dispatchSplitSize_; //!< Dispath split size in elements
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};
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public:
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VirtualGPU(Device& device);
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//! Creates virtual gpu object
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bool create(bool profiling, //!< Enables profilng on the queue
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uint deviceQueueSize = 0, //!< Device queue size, 0 if host queue
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uint rtCUs = amd::CommandQueue::RealTimeDisabled,
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amd::CommandQueue::Priority priority = amd::CommandQueue::Priority::Normal);
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~VirtualGPU();
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void submitReadMemory(amd::ReadMemoryCommand& vcmd);
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void submitWriteMemory(amd::WriteMemoryCommand& vcmd);
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void submitCopyMemory(amd::CopyMemoryCommand& vcmd);
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void submitCopyMemoryP2P(amd::CopyMemoryP2PCommand& vcmd);
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void submitMapMemory(amd::MapMemoryCommand& vcmd);
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void submitUnmapMemory(amd::UnmapMemoryCommand& vcmd);
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void submitKernel(amd::NDRangeKernelCommand& vcmd);
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bool submitKernelInternal(
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const amd::NDRangeContainer& sizes, //!< Workload sizes
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const amd::Kernel& kernel, //!< Kernel for execution
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const_address parameters, //!< Parameters for the kernel
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bool nativeMem = true, //!< Native memory objects
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amd::Event* enqueueEvent = nullptr, //!< Event provided in the enqueue kernel command
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uint32_t sharedMemBytes = 0, //!< Shared memory size
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bool cooperativeGroups = false //!< TRUE if cooperative groups mode is required
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);
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void submitNativeFn(amd::NativeFnCommand& vcmd);
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void submitFillMemory(amd::FillMemoryCommand& vcmd);
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void submitMigrateMemObjects(amd::MigrateMemObjectsCommand& cmd);
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void submitMarker(amd::Marker& vcmd);
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void submitAcquireExtObjects(amd::AcquireExtObjectsCommand& vcmd);
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void submitReleaseExtObjects(amd::ReleaseExtObjectsCommand& vcmd);
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void submitPerfCounter(amd::PerfCounterCommand& vcmd);
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void submitThreadTraceMemObjects(amd::ThreadTraceMemObjectsCommand& cmd);
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void submitThreadTrace(amd::ThreadTraceCommand& vcmd);
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void submitSignal(amd::SignalCommand& vcmd);
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void submitMakeBuffersResident(amd::MakeBuffersResidentCommand& vcmd);
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virtual void submitSvmFreeMemory(amd::SvmFreeMemoryCommand& cmd);
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virtual void submitSvmCopyMemory(amd::SvmCopyMemoryCommand& cmd);
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virtual void submitSvmFillMemory(amd::SvmFillMemoryCommand& cmd);
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virtual void submitSvmMapMemory(amd::SvmMapMemoryCommand& cmd);
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virtual void submitSvmUnmapMemory(amd::SvmUnmapMemoryCommand& cmd);
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virtual void submitTransferBufferFromFile(amd::TransferBufferFileCommand& cmd);
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void releaseMemory(GpuMemoryReference* mem);
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void flush(amd::Command* list = nullptr, bool wait = false);
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//! Returns GPU device object associated with this kernel
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const Device& dev() const { return gpuDevice_; }
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//! Set the last known GPU event
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void setGpuEvent(GpuEvent gpuEvent, //!< GPU event for tracking
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bool flush = false //!< TRUE if flush is required
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);
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//! Flush DMA buffer on the specified engine
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void flushDMA(uint engineID //!< Engine ID for DMA flush
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);
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//! Wait for all engines on this Virtual GPU
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//! Returns TRUE if CPU didn't wait for GPU
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bool waitAllEngines(CommandBatch* cb = nullptr //!< Command batch
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);
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//! Waits for the latest GPU event with a lock to prevent multiple entries
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void waitEventLock(CommandBatch* cb //!< Command batch
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);
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//! Returns a resource associated with the constant buffer
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const ConstantBuffer* cb(uint idx) const { return constBufs_[idx]; }
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//! Adds CAL objects into the constant buffer vector
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void addConstBuffer(ConstantBuffer* cb) { constBufs_.push_back(cb); }
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//! Start the command profiling
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void profilingBegin(amd::Command& command, //!< Command queue object
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bool drmProfiling = false //!< Measure DRM time
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);
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//! End the command profiling
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void profilingEnd(amd::Command& command);
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//! Collect the profiling results
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bool profilingCollectResults(CommandBatch* cb, //!< Command batch
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const amd::Event* waitingEvent //!< Waiting event
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);
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//! Embeds memory handle info into the CB associated with this VGPU
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inline void logVmMemory(const std::string name, //!< Brief description of the memory object
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const Memory* memory //!< GPU memory object
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);
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//! Adds a memory handle into the PAL memory array for Virtual Heap
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inline void addVmMemory(const Memory* memory //!< GPU memory object
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);
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//! Adds the last submitted kernel to the queue for tracking a possible hang
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inline void AddKernel(const amd::Kernel& kernel //!< AMD kernel object
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) const;
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//! Checks if runtime dispatches the same kernel as previously
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inline bool IsSameKernel(const amd::Kernel& kernel //!< AMD kernel object
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) const;
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//! Adds a dopp desktop texture reference
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void addDoppRef(const Memory* memory, //!< GPU memory object
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bool lastDoopCmd, //!< is the last submission for the pre-present primary
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bool pfpaDoppCmd //!< is a submission for the pre-present primary
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);
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//! Return xfer buffer for staging operations
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XferBuffer& xferWrite() { return writeBuffer_; }
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//! Return managed buffer for staging operations
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ManagedBuffer& managedBuffer() { return managedBuffer_; }
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//! Adds a pinned memory object into a map
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void addPinnedMem(amd::Memory* mem);
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//! Release pinned memory objects
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void releasePinnedMem();
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//! Finds if pinned memory is cached
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amd::Memory* findPinnedMem(void* addr, size_t size);
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//! Get the PrintfDbgHSA object
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PrintfDbgHSA& printfDbgHSA() const { return *printfDbgHSA_; }
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//! Enables synchronized transfers
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void enableSyncedBlit() const;
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//! Checks if profiling is enabled
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bool profiling() const { return state_.profiling_; }
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//! Returns memory dependency class
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MemoryDependency& memoryDependency() { return memoryDependency_; }
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//! Returns hsaQueueMem_
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const Memory* hsaQueueMem() const { return hsaQueueMem_; }
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//! Returns DMA flush management structure
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const DmaFlushMgmt& dmaFlushMgmt() const { return dmaFlushMgmt_; }
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//! Returns the HW ring used on this virtual device
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uint hwRing() const { return hwRing_; }
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//! Returns virtual queue object for device enqueuing
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Memory* vQueue() const { return virtualQueue_; }
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//! Update virtual queue header
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void writeVQueueHeader(VirtualGPU& hostQ, const Memory* kernelTable);
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//! Returns TRUE if virtual queue was successfully allocatted
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bool createVirtualQueue(uint deviceQueueSize //!< Device queue size
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);
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EngineType engineID_; //!< Engine ID for this VirtualGPU
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//! Returns PAL command buffer interface
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Pal::ICmdBuffer* iCmd() const {
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Queue* queue = queues_[engineID_];
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return queue->iCmd();
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}
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//! Returns true if the provided command buffer is the active one
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bool isActiveCmd(Pal::ICmdBuffer* iCmd) const {
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return (queues_[engineID_] != nullptr) && (iCmd == queues_[engineID_]->iCmd()) ? true : false;
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}
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//! Returns queue, associated with VirtualGPU
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Queue& queue(EngineType id) const { return *queues_[id]; }
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void addBarrier(RgpSqqtBarrierReason reason = RgpSqqtBarrierReason::Unknown,
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bool flushL2 = false) const {
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Pal::BarrierInfo barrier = {};
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barrier.pipePointWaitCount = 1;
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Pal::HwPipePoint point = Pal::HwPipePostCs;
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barrier.pPipePoints = &point;
|
|
barrier.transitionCount = 1;
|
|
uint32_t cacheMask = (flushL2) ? Pal::CoherCopy : Pal::CoherShader;
|
|
Pal::BarrierTransition trans = {cacheMask,
|
|
cacheMask,
|
|
{nullptr,
|
|
{{0, 0, 0}, 0, 0, 0},
|
|
Pal::LayoutShaderRead,
|
|
Pal::LayoutShaderRead}};
|
|
barrier.pTransitions = &trans;
|
|
barrier.waitPoint = Pal::HwPipePreCs;
|
|
barrier.reason = static_cast<uint32_t>(reason);
|
|
iCmd()->CmdBarrier(barrier);
|
|
queues_[engineID_]->submit<true>(false);
|
|
}
|
|
|
|
void eventBegin(EngineType engId) const {
|
|
const static bool Begin = true;
|
|
profileEvent(engId, Begin);
|
|
}
|
|
|
|
void eventEnd(EngineType engId, GpuEvent& event, bool forceExec = false) const {
|
|
constexpr bool End = false;
|
|
if (forceExec) {
|
|
constexpr bool ForceFlush = true;
|
|
event.id_ = queues_[engId]->submit(ForceFlush);
|
|
profileEvent(engId, End);
|
|
} else {
|
|
profileEvent(engId, End);
|
|
event.id_ = queues_[engId]->submit(GPU_FLUSH_ON_EXECUTION);
|
|
}
|
|
event.engineId_ = engId;
|
|
}
|
|
|
|
void waitForEvent(GpuEvent* event) const {
|
|
if (event->isValid()) {
|
|
assert(event->engineId_ < AllEngines);
|
|
queues_[event->engineId_]->waitForEvent(event->id_);
|
|
event->invalidate();
|
|
}
|
|
}
|
|
|
|
bool isDone(GpuEvent* event) {
|
|
if (event->isValid()) {
|
|
assert(event->engineId_ < AllEngines);
|
|
if (queues_[event->engineId_]->isDone(event->id_)) {
|
|
event->invalidate();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
//! Returns TRUE if SDMA requires overlap synchronizaiton
|
|
bool validateSdmaOverlap(const Resource& src, //!< Source resource for SDMA transfer
|
|
const Resource& dst //!< Destination resource for SDMA transfer
|
|
);
|
|
|
|
//! Checks if RGP capture is enabled
|
|
bool rgpCaptureEna() const { return state_.rgpCaptureEnabled_; }
|
|
|
|
//! Waits for idle on compute engine
|
|
void WaitForIdleCompute() {
|
|
if (events_[MainEngine].isValid()) {
|
|
queues_[events_[MainEngine].engineId_]->waitForEvent(events_[MainEngine].id_);
|
|
events_[MainEngine].invalidate();
|
|
}
|
|
}
|
|
|
|
void* getOrCreateHostcallBuffer();
|
|
|
|
protected:
|
|
void profileEvent(EngineType engine, bool type) const;
|
|
|
|
//! Creates buffer object from image
|
|
amd::Memory* createBufferFromImage(
|
|
amd::Memory& amdImage //! The parent image object(untiled images only)
|
|
);
|
|
|
|
private:
|
|
struct MemoryRange {
|
|
uint64_t start_; //!< Memory range start address
|
|
uint64_t end_; //!< Memory range end address
|
|
MemoryRange() : start_(0), end_(0) {}
|
|
};
|
|
|
|
//! Allocates constant buffers
|
|
bool allocConstantBuffers();
|
|
|
|
//! Allocate hsaQueueMem_
|
|
bool allocHsaQueueMem();
|
|
|
|
//! Awaits a command batch with a waiting event
|
|
bool awaitCompletion(CommandBatch* cb, //!< Command batch for to wait
|
|
const amd::Event* waitingEvent = nullptr //!< A waiting event
|
|
);
|
|
|
|
//! Detects memory dependency for HSAIL kernels and flushes caches
|
|
bool processMemObjectsHSA(const amd::Kernel& kernel, //!< AMD kernel object for execution
|
|
const_address params, //!< Pointer to the param's store
|
|
bool nativeMem, //!< Native memory objects
|
|
size_t& ldsAddess //!< Returns LDS size, used in the kernel
|
|
);
|
|
|
|
//! Common function for fill memory used by both svm Fill and non-svm fill
|
|
bool fillMemory(cl_command_type type, //!< the command type
|
|
amd::Memory* amdMemory, //!< memory object to fill
|
|
const void* pattern, //!< pattern to fill the memory
|
|
size_t patternSize, //!< pattern size
|
|
const amd::Coord3D& origin, //!< memory origin
|
|
const amd::Coord3D& size //!< memory size for filling
|
|
);
|
|
|
|
bool copyMemory(cl_command_type type, //!< the command type
|
|
amd::Memory& srcMem, //!< source memory object
|
|
amd::Memory& dstMem, //!< destination memory object
|
|
bool entire, //!< flag of entire memory copy
|
|
const amd::Coord3D& srcOrigin, //!< source memory origin
|
|
const amd::Coord3D& dstOrigin, //!< destination memory object
|
|
const amd::Coord3D& size, //!< copy size
|
|
const amd::BufferRect& srcRect, //!< region of source for copy
|
|
const amd::BufferRect& dstRect //!< region of destination for copy
|
|
);
|
|
|
|
void buildKernelInfo(const HSAILKernel& hsaKernel, //!< hsa kernel
|
|
hsa_kernel_dispatch_packet_t* aqlPkt, //!< aql packet for dispatch
|
|
HwDbgKernelInfo& kernelInfo, //!< kernel info for the dispatch
|
|
amd::Event* enqueueEvent //!< Event provided in the enqueue kernel command
|
|
);
|
|
|
|
void assignDebugTrapHandler(const DebugToolInfo& dbgSetting, //!< debug settings
|
|
HwDbgKernelInfo& kernelInfo //!< kernel info for the dispatch
|
|
);
|
|
|
|
void PrintChildren(const HSAILKernel& hsaKernel, //!< The parent HSAIL kernel
|
|
VirtualGPU* gpuDefQueue //!< Device queue for children execution
|
|
);
|
|
|
|
bool PreDeviceEnqueue(const amd::Kernel& kernel, //!< Parent amd kernel object
|
|
const HSAILKernel& hsaKernel, //!< Parent HSAIL object
|
|
VirtualGPU** gpuDefQueue, //!< [Return] GPU default queue
|
|
uint64_t* vmDefQueue //!< [Return] VM handle to the virtual queue
|
|
);
|
|
|
|
void PostDeviceEnqueue(
|
|
const amd::Kernel& kernel, //!< Parent amd kernel object
|
|
const HSAILKernel& hsaKernel, //!< Parent HSAIL object
|
|
VirtualGPU* gpuDefQueue, //!< GPU default queue
|
|
uint64_t vmDefQueue, //!< VM handle to the virtual queue
|
|
uint64_t vmParentWrap, //!< VM handle to the wrapped AQL packet location
|
|
GpuEvent* gpuEvent //!< [Return] GPU event associated with the device enqueue
|
|
);
|
|
|
|
Device& gpuDevice_; //!< physical GPU device
|
|
|
|
PrintfDbgHSA* printfDbgHSA_; //!< HSAIL printf implemenation
|
|
|
|
TimeStampCache* tsCache_; //!< TimeStamp cache
|
|
MemoryDependency memoryDependency_; //!< Memory dependency class
|
|
|
|
DmaFlushMgmt dmaFlushMgmt_; //!< DMA flush management
|
|
|
|
std::vector<amd::Memory*> pinnedMems_; //!< Pinned memory list
|
|
|
|
ManagedBuffer managedBuffer_; //!< Managed write buffer
|
|
constbufs_t constBufs_; //!< constant buffers
|
|
XferBuffer writeBuffer_; //!< Transfer/staging buffer for uploads
|
|
|
|
typedef std::queue<CommandBatch*> CommandBatchQueue;
|
|
CommandBatchQueue cbQueue_; //!< Queue of command batches
|
|
CommandBatchQueue freeCbQueue_; //!< Queue of free command batches
|
|
|
|
uint hwRing_; //!< HW ring used on this virtual device
|
|
|
|
State state_; //!< virtual GPU current state
|
|
GpuEvent events_[AllEngines]; //!< Last known GPU events
|
|
|
|
uint64_t readjustTimeGPU_; //!< Readjust time between GPU and CPU timestamps
|
|
TimeStamp* lastTS_; //!< Last timestamp executed on Virtual GPU
|
|
TimeStamp* profileTs_; //!< current profiling timestamp for command
|
|
|
|
AmdVQueueHeader* vqHeader_; //!< Sysmem copy for virtual queue header
|
|
Memory* virtualQueue_; //!< Virtual device queue
|
|
Memory* schedParams_; //!< The scheduler parameters
|
|
uint deviceQueueSize_; //!< Device queue size
|
|
uint maskGroups_; //!< The number of mask groups processed in the scheduler by one thread
|
|
|
|
Memory* hsaQueueMem_; //!< Memory for the amd_queue_t object
|
|
Pal::ICmdAllocator* cmdAllocator_; //!< Command buffer allocator
|
|
Queue* queues_[AllEngines]; //!< HW queues for all engines
|
|
MemoryRange sdmaRange_; //!< SDMA memory range for write access
|
|
std::vector<Image*> wrtBackImageBuffer_; //!< Array of images for write back
|
|
|
|
void* hostcallBuffer_; //!< Hostcall buffer
|
|
};
|
|
|
|
inline void VirtualGPU::logVmMemory(const std::string name, const Memory* memory) {
|
|
if (PAL_EMBED_KERNEL_MD || (AMD_LOG_LEVEL >= amd::LOG_INFO)) {
|
|
char buf[256];
|
|
sprintf(buf,
|
|
"%s = ptr:[%p-%p] obj:[%p-%p]",
|
|
name.c_str(),
|
|
reinterpret_cast<void*>(memory->vmAddress()),
|
|
reinterpret_cast<void*>(memory->vmAddress() + memory->size()),
|
|
reinterpret_cast<void*>(memory->iMem()->Desc().gpuVirtAddr),
|
|
reinterpret_cast<void*>(memory->iMem()->Desc().gpuVirtAddr + memory->iMem()->Desc().size));
|
|
if (PAL_EMBED_KERNEL_MD) {
|
|
iCmd()->CmdCommentString(buf);
|
|
}
|
|
LogPrintfInfo("%s threadId : %zx\n", buf, std::this_thread::get_id());
|
|
}
|
|
}
|
|
|
|
inline void VirtualGPU::addVmMemory(const Memory* memory) {
|
|
queues_[MainEngine]->addCmdMemRef(memory->memRef());
|
|
memory->setBusy(*this, queues_[MainEngine]->cmdBufId());
|
|
}
|
|
|
|
inline void VirtualGPU::AddKernel(const amd::Kernel& kernel) const {
|
|
queues_[MainEngine]->last_kernel_ = &kernel;
|
|
}
|
|
|
|
inline bool VirtualGPU::IsSameKernel(const amd::Kernel& kernel) const {
|
|
return (queues_[MainEngine]->last_kernel_ == &kernel) ? true : false;
|
|
}
|
|
|
|
template <bool avoidBarrierSubmit> uint VirtualGPU::Queue::submit(bool forceFlush) {
|
|
cmdCnt_++;
|
|
uint id = cmdBufIdCurrent_;
|
|
bool flushCmd = ((cmdCnt_ > MaxCommands) || forceFlush) && !avoidBarrierSubmit;
|
|
if (flushCmd) {
|
|
if (!flush()) {
|
|
return GpuEvent::InvalidID;
|
|
}
|
|
}
|
|
return id;
|
|
}
|
|
|
|
template <typename T>
|
|
inline void WriteAqlArgAt(unsigned char* dst, //!< The write pointer to the buffer
|
|
const T* src, //!< The source pointer
|
|
uint size, //!< The size in bytes to copy
|
|
size_t offset //!< The alignment to follow while writing to the buffer
|
|
) {
|
|
memcpy(dst + offset, src, size);
|
|
}
|
|
|
|
template <>
|
|
inline void WriteAqlArgAt(unsigned char* dst, //!< The write pointer to the buffer
|
|
const uint32_t* src, //!< The source pointer
|
|
uint size, //!< The size in bytes to copy
|
|
size_t offset //!< The alignment to follow while writing to the buffer
|
|
) {
|
|
*(reinterpret_cast<uint32_t*>(dst + offset)) = *src;
|
|
}
|
|
|
|
template <>
|
|
inline void WriteAqlArgAt(unsigned char* dst, //!< The write pointer to the buffer
|
|
const uint64_t* src, //!< The source pointer
|
|
uint size, //!< The size in bytes to copy
|
|
size_t offset //!< The alignment to follow while writing to the buffer
|
|
) {
|
|
*(reinterpret_cast<uint64_t*>(dst + offset)) = *src;
|
|
}
|
|
/*@}*/ // namespace pal
|
|
} // namespace pal
|