foreman
8af44388e9
ECR #354633 - SPIR-V: Disable cl_khr_il_program until conformance test is updated to allow it. Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/cpu/cpusettings.cpp#32 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/hsa/hsasettings.cpp#39 edit ... //depot/stg/opencl/drivers/opencl/tests/conformance/devel/2.0/test_conformance/spirv/main.cpp#8 edit
106 wiersze
3.3 KiB
C++
106 wiersze
3.3 KiB
C++
//
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// Copyright 2011 Advanced Micro Devices, Inc. All rights reserved.
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//
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#include "device/cpu/cpusettings.hpp"
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#include "os/os.hpp"
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namespace cpu {
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bool
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Settings::create()
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{
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// This code is temporary until cl_khr_fp64 is unconditional
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if (flagIsDefault(CL_KHR_FP64) || CL_KHR_FP64) {
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enableExtension(ClKhrFp64);
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}
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enableExtension(ClAmdFp64);
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enableExtension(ClKhrGlobalInt32BaseAtomics);
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enableExtension(ClKhrGlobalInt32ExtendedAtomics);
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enableExtension(ClKhrLocalInt32BaseAtomics);
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enableExtension(ClKhrLocalInt32ExtendedAtomics);
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#ifdef _LP64
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enableExtension(ClKhrInt64BaseAtomics);
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enableExtension(ClKhrInt64ExtendedAtomics);
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#endif // _LP64
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enableExtension(ClKhrByteAddressableStore);
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enableExtension(ClKhrGlSharing);
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enableExtension(ClKhrGlEvent);
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enableExtension(ClExtDeviceFission);
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enableExtension(ClAmdDeviceAttributeQuery);
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enableExtension(ClAmdVec3);
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enableExtension(ClAmdMediaOps);
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enableExtension(ClAmdMediaOps2);
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enableExtension(ClAmdPopcnt);
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enableExtension(ClAmdPrintf);
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// enableExtension(ClKhrSelectFpRoundingMode);
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enableExtension(ClKhr3DImageWrites);
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// enableExtension(ClKhrFp16);
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#if defined(_WIN32)
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enableExtension(ClKhrD3d10Sharing);
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#endif // _WIN32
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enableExtension(ClKhrSpir);
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// ToDo: enable this after conformance test is updated to accept it
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// enableExtension(ClKhrIlProgram);
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// Enable some OpenCL 2.0 extensions
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if ((OPENCL_MAJOR >= 2) && (CPU_OPENCL_VERSION >= 200)) {
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partialDispatch_ = true;
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enableExtension(ClKhrSubGroups);
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supportDepthsRGB_ = true;
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enableExtension(ClKhrDepthImages);
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}
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// Map CPUID feature bits to our own feature bits
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const int sse2_features = CPUFEAT_DX_SSE | CPUFEAT_DX_SSE2;
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const int avx_features = CPUFEAT_CX_SSE3 | CPUFEAT_CX_SSSE3 |
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CPUFEAT_CX_SSE4_1 | CPUFEAT_CX_SSE4_2 |
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CPUFEAT_CX_POPCNT | CPUFEAT_CX_AVX |
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CPUFEAT_CX_OSXSAVE;
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const int fma3_features = INTEL_CPUFEAT_CX_FMA3;
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const int fma4_features = AMD_CPUFEAT_CX_FMA4 | AMD_CPUFEAT_CX_XOP;
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int regs[4];
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#if defined(ATI_ARCH_X86)
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amd::Os::cpuid(regs, 0x0);
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bool isAmd = regs[1] == ('A' | ('u' << 8) | ('t' << 16) | ('h' << 24));
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bool isIntel = regs[1] == ('G' | ('e' << 8) | ('n' << 16) | ('u' << 24));
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amd::Os::cpuid(regs, 0x1);
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cpuFeatures_ = (regs[3] & sse2_features) == sse2_features ?
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SSE2Instructions : 0;
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if ((regs[2] & avx_features) == avx_features) {
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// Check for state support
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uint64_t xcr0 = amd::Os::xgetbv(0);
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// Check for SSE and YMM bits (1 and 2)
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if (((uint32_t)xcr0 & 0x6U) == 0x6U) {
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cpuFeatures_ |= AVXInstructions;
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// Now check for FMA and XOP
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if (isIntel) {
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cpuFeatures_ |= (regs[2] & fma3_features) == fma3_features ?
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FMA3Instructions : 0;
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}
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if (isAmd) {
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amd::Os::cpuid(regs, 0x80000001);
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cpuFeatures_ |= (regs[2] & fma4_features) == fma4_features ?
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FMA4Instructions : 0;
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}
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}
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}
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#endif // ATI_ARCH_X86
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return true;
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}
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} // namespace cpu
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