amilanov-amd
186 líneas
7.7 KiB
C++
186 líneas
7.7 KiB
C++
/*
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Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#include "arithmetic_common.hh"
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#include <hip_test_common.hh>
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/**
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* @addtogroup atomicSub_system atomicSub_system
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* @{
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* @ingroup AtomicsTest
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*/
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/**
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* Test Description
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* ------------------------
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* - Executes a kernel two times concurrently on a two devices wherein all threads will perform
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* an atomic addition on a target memory location. Each thread will add the same value to the memory
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* location, storing the return value into a separate output array slot corresponding to it. Once
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* complete, the output array and target memory is validated to contain all the expected values.
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* Several memory access patterns are tested:
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* -# All threads subtract from a single, compile time deducible, memory location
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* -# Each thread targets an array containing warp_size elements, using tid % warp_size
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* for indexing
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* -# Same as the above, but the elements are spread out by L1 cache line size bytes.
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*
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* - The test is run for:
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* - All overloads of atomicSub_system
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* - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory
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* - Several grid and block dimension combinations.
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* Test source
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* ------------------------
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* - unit/atomics/atomicSub_system.cc
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* Test requirements
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* ------------------------
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* - HIP_VERSION >= 5.2
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*/
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TEMPLATE_TEST_CASE("Unit_atomicSub_system_Positive_Peer_GPUs", "[multigpu]",
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int, unsigned int, unsigned long, unsigned long long, float,
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double) {
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int warp_size = 0;
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HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
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const auto cache_line_size = 128u;
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for (auto current = 0; current < 1; ++current) {
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DYNAMIC_SECTION("Same address " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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2, 2, 1, sizeof(TestType));
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}
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DYNAMIC_SECTION("Adjacent addresses " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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2, 2, warp_size, sizeof(TestType));
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}
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DYNAMIC_SECTION("Scattered addresses " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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2, 2, warp_size, cache_line_size);
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}
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}
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}
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/**
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* Test Description
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* ------------------------
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* - Executes a kernel on a single device wherein all threads will perform
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* an atomic addition on a target memory location. Each thread will add the same value to the
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* memory location, storing the return value into a separate output array slot corresponding to
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* it. While the kernel is running, the host performs atomic additions, in 4 threads, on the same
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* memory location(s). Once complete, the output array and target memory is validated to contain
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* all the expected values. Several memory access patterns are tested:
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* -# All threads subtract from a single, compile time deducible, memory location
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* -# Each thread targets an array containing warp_size elements, using tid % warp_size
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* for indexing
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* -# Same as the above, but the elements are spread out by L1 cache line size bytes.
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*
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* - The test is run for:
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* - All overloads of atomicSub_system
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* - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory
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* - Several grid and block dimension combinations.
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* Test source
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* ------------------------
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* - unit/atomics/atomicSub_system.cc
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* Test requirements
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* ------------------------
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* - HIP_VERSION >= 5.2
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*/
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TEMPLATE_TEST_CASE("Unit_atomicSub_system_Positive_Host_And_GPU", "[multigpu]",
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int, unsigned int, unsigned long, unsigned long long, float,
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double) {
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int warp_size = 0;
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HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
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const auto cache_line_size = 128u;
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for (auto current = 0; current < 1; ++current) {
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DYNAMIC_SECTION("Same address " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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1, 1, 1, sizeof(TestType), 4);
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}
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DYNAMIC_SECTION("Adjacent addresses " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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1, 1, warp_size, sizeof(TestType), 4);
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}
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DYNAMIC_SECTION("Scattered addresses " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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1, 1, warp_size, cache_line_size, 4);
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}
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}
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}
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/**
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* Test Description
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* ------------------------
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* - Executes a kernel two times on two devices wherein all threads will perform
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* an atomic addition on a target memory location. Each thread will add the same value to the
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* memory location, storing the return value into a separate output array slot corresponding to
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* it. While the kernel is running, the host performs atomic additions, in 4 threads, on the same
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* memory location(s). Once complete, the output array and target memory is validated to contain
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* all the expected values. Several memory access patterns are tested:
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* -# All threads subtract from a single, compile time deducible, memory location
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* -# Each thread targets an array containing warp_size elements, using tid % warp_size
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* for indexing
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* -# Same as the above, but the elements are spread out by L1 cache line size bytes.
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*
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* - The test is run for:
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* - All overloads of atomicSub_system
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* - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory
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* - Several grid and block dimension combinations.
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* Test source
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* ------------------------
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* - unit/atomics/atomicSub_system.cc
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* Test requirements
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* ------------------------
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* - HIP_VERSION >= 5.2
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*/
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TEMPLATE_TEST_CASE("Unit_atomicSub_system_Positive_Host_And_Peer_GPUs",
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"[multigpu]", int, unsigned int, unsigned long,
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unsigned long long, float, double) {
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int warp_size = 0;
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HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
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const auto cache_line_size = 128u;
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for (auto current = 0; current < 1; ++current) {
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DYNAMIC_SECTION("Same address " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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2, 2, 1, sizeof(TestType), 4);
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}
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DYNAMIC_SECTION("Adjacent addresses " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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2, 2, warp_size, sizeof(TestType), 4);
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}
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DYNAMIC_SECTION("Scattered addresses " << current) {
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MultipleDeviceMultipleKernelAndHostTest<TestType, AtomicOperation::kSubSystem>(
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2, 2, warp_size, cache_line_size, 4);
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}
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}
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}
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/**
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* End doxygen group AtomicsTest.
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* @}
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*/
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