Files
rocm-systems/tests/workloads/SPI/mi100/prev_analysis/602.csv
T
JoseSantosAMD 717a21cf84 Update csv headers, and SystemExit codes
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>
2024-02-04 12:44:47 -06:00

656 B

1MetricAvgMinMaxUnit
2Wave request Failed (CS)325734.568862275456281015602Cycles
3CS Stall19499.9820359281440692932Cycles
4CS Stall Rate5.1235687037318980.076.57155612428132Pct
5Scratch Stall0.000Cycles
6Insufficient SIMD Waveslots59217.119760479040772162Simd
7Insufficient SIMD VGPRs610425.4730538923036746998Simd
8Insufficient SIMD SGPRs0.000Simd
9Insufficient CU LDS_Per_Workgroup0.000Cu
10Insufficient CU Barries0.000Cu
11Insufficient Bulky Resource0.000Cu
12Reach CU Threadgroups Limit0.000Cycles
13Reach CU Wave Limit0.000Cycles
14VGPR Writes4.04.04.0Cycles/wave
15SGPR Writes5.0059880239520965.06.0Cycles/wave