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rocm-systems/tests/workloads/mixbench/mi100/prev_analysis/602.csv
T
JoseSantosAMD 717a21cf84 Update csv headers, and SystemExit codes
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>
2024-02-04 12:44:47 -06:00

656 B

1MetricAvgMinMaxUnit
2Wave request Failed (CS)330137.6586826347629924758Cycles
3CS Stall18882.90419161676601047959Cycles
4CS Stall Rate4.6358432951553910.0116.03428460071794Pct
5Scratch Stall0.000Cycles
6Insufficient SIMD Waveslots53994.514970059880695554Simd
7Insufficient SIMD VGPRs598051.6107784432048149082Simd
8Insufficient SIMD SGPRs0.000Simd
9Insufficient CU LDS_Per_Workgroup0.000Cu
10Insufficient CU Barries0.000Cu
11Insufficient Bulky Resource0.000Cu
12Reach CU Threadgroups Limit0.000Cycles
13Reach CU Wave Limit0.000Cycles
14VGPR Writes4.04.04.0Cycles/wave
15SGPR Writes5.0059880239520965.06.0Cycles/wave