Evgeny
7c4369bde4
Contributors:
Ammar ELWazir <aelwazir@amd.com>
AravindanC <aravindan.cheruvally@amd.com>
Benjamin Welton <bewelton@amd.com>
Ma, Bing <Bing.Ma@amd.com>
Chun Yang <chun.yang@amd.com>
Cole Nelson <cole.nelson@amd.com>
Ethan Stewart <ethan.stewart@amd.com>
Evgeny <evgeny.shcherbakov@amd.com>
Freddy Paul <Freddy.paul@amd.com>
Giovanni Baraldi <gbaraldi@amd.com>
Gopesh Bhardwaj <Gopesh.Bhardwaj@amd.com>
Icarus Sparry <icarus.sparry@amd.com>
itrowbri <Ian.Trowbridge@amd.com>
James Edwards <JamesAdrian.Edwards@amd.com>
jatang <jatang@amd.com>
Jeremy Newton <Jeremy.Newton@amd.com>
Jonathan Kim <jonathan.kim@amd.com>
Kent Russell <kent.russell@amd.com>
Kiumars Sabeti <kiumars.sabeti@amd.com>
Lang Yu <lang.yu@amd.com>
Laurent Morichetti <laurent.morichetti@amd.com>
Mallya, Ameya Keshava <AmeyaKeshava.Mallya@amd.com>
Manjunath Jakaraddi <manjunath.jakaraddi@amd.com>
Mark Laws <markdavid.laws@amd.com>
Mohan Kumar Mithur <Mohan.KumarMithur@amd.com>
Nicholas Curtis <nicurtis@amd.com>
Nirmal Unnikrishnan <Nirmal.Unnikrishnan@amd.com>
Parag Bhandari <parag.bhandari@amd.com>
Ranjith Ramakrishnan <Ranjith.Ramakrishnan@amd.com>
Robert Gregory <Robert.Gregory@amd.com>
Saravanan Solaiyappan <saravanan.solaiyappan@amd.com>
Saurabh Verma <saurabh.verma@amd.com>
Srihari Uttanur <srihari.u@amd.com>
Srinivasan Subramanian <srinivasan.subramanian@amd.com>
Sriraksha Nagaraj <Sriraksha.Nagaraj@amd.com>
Sushma Vaddireddy <svaddire@amd.com>
Xianwei Zhang <Xianwei.Zhang@amd.com>
[ROCm/aqlprofile commit: 1ed169e30c]
218 라인
8.8 KiB
C++
218 라인
8.8 KiB
C++
// MIT License
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//
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// Copyright (c) 2017-2025 Advanced Micro Devices, Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#ifndef _GFX11_BLOCKINFO_H_
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#define _GFX11_BLOCKINFO_H_
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namespace gfxip {
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namespace gfx11 {
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// To define GFX11 specific blocks info like GC caches blocks
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// All common with GFX9 blocks are inherited from GFX9 space
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// Enumeration of Gfx9 hardware counter blocks
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enum CounterBlockId {
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CbCounterBlockId,
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CpcCounterBlockId,
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CpfCounterBlockId,
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CpgCounterBlockId,
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DbCounterBlockId,
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GdsCounterBlockId,
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GrbmCounterBlockId,
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GrbmSeCounterBlockId,
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// IaCounterBlockId,
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// PaScCounterBlockId,
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// PaSuCounterBlockId,
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SpiCounterBlockId,
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SqCounterBlockId,
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SqGsCounterBlockId,
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// SqVsCounterBlockId,
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SqPsCounterBlockId,
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SqHsCounterBlockId,
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SqCsCounterBlockId,
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SxCounterBlockId,
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TaCounterBlockId,
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// TcaCounterBlockId,
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// TccCounterBlockId,
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// TcsCounterBlockId,
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TdCounterBlockId,
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// VgtCounterBlockId,
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// WdCounterBlockId,
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// MC blocks
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GceaCounterBlockId,
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// AtcCounterBlockId,
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// AtcL2CounterBlockId,
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// McVmL2CounterBlockId,
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RpbCounterBlockId,
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RmiCounterBlockId,
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Gl1aCounterBlockId,
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Gl1cCounterBlockId,
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Gl2aCounterBlockId,
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Gl2cCounterBlockId,
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GcrCounterBlockId,
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GusCounterBlockId,
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// SDMA block
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Sdma0CounterBlockId,
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Sdma1CounterBlockId,
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// UMC block
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UmcCounterBlockId,
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// Counters retrieved by KFD
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IommuV2CounterBlockId,
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KernelDriverCounterBlockId,
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CpPipeStatsCounterBlockId,
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TcpCounterBlockId,
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HwInfoCounterBlockId,
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FirstCounterBlockId = CbCounterBlockId,
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LastCounterBlockId = HwInfoCounterBlockId,
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};
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/*
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* SPM global and shader engine block IDs
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*/
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enum SpmGlobalBlockId {
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SPM_GLOBAL_BLOCK_NAME_CPG = 0,
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SPM_GLOBAL_BLOCK_NAME_CPC = 1,
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SPM_GLOBAL_BLOCK_NAME_CPF = 2,
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SPM_GLOBAL_BLOCK_NAME_GDS = 3,
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SPM_GLOBAL_BLOCK_NAME_TCC = 4,
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SPM_GLOBAL_BLOCK_NAME_TCA = 5,
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SPM_GLOBAL_BLOCK_NAME_IA = 6,
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SPM_GLOBAL_BLOCK_NAME_TCS = 7,
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};
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enum SpmSeBlockId {
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SPM_SE_BLOCK_NAME_CB = 0,
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SPM_SE_BLOCK_NAME_DB = 1,
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SPM_SE_BLOCK_NAME_PA = 2,
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SPM_SE_BLOCK_NAME_SX = 3,
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SPM_SE_BLOCK_NAME_SC = 4,
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SPM_SE_BLOCK_NAME_TA = 5,
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SPM_SE_BLOCK_NAME_TD = 6,
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SPM_SE_BLOCK_NAME_TCP = 7,
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SPM_SE_BLOCK_NAME_SPI = 8,
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SPM_SE_BLOCK_NAME_SQG = 9,
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SPM_SE_BLOCK_NAME_VGT = 10,
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};
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// Number of block instances
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static const uint32_t CbCounterBlockNumInstances = 4;
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static const uint32_t DbCounterBlockNumInstances = 4;
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static const uint32_t TaCounterBlockNumInstances = 16;
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static const uint32_t TdCounterBlockNumInstances = 16;
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static const uint32_t TcpCounterBlockNumInstances = 16;
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static const uint32_t TcaCounterBlockNumInstances = 2;
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static const uint32_t TccCounterBlockNumInstances = 16;
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static const uint32_t SdmaCounterBlockNumInstances = 2;
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// MI100 has 8 SDMA instances
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static const uint32_t SdmaCounterBlockMaxInstances = 8;
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static const uint32_t UmcCounterBlockMaxInstances = 32;
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static const uint32_t RmiCounterBlockNumInstances = 8;
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static const uint32_t GceaCounterBlockNumInstances = 16;
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// Number of block counter registers
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static const uint32_t CbCounterBlockNumCounters = 4;
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static const uint32_t CpcCounterBlockNumCounters = 2;
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static const uint32_t CpfCounterBlockNumCounters = 2;
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static const uint32_t CpgCounterBlockNumCounters = 2;
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static const uint32_t DbCounterBlockNumCounters = 4;
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static const uint32_t GdsCounterBlockNumCounters = 4;
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static const uint32_t GrbmCounterBlockNumCounters = 2;
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static const uint32_t GrbmSeCounterBlockNumCounters = 4;
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static const uint32_t IaCounterBlockNumCounters = 4;
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static const uint32_t PaSuCounterBlockNumCounters = 4;
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static const uint32_t PaScCounterBlockNumCounters = 8;
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static const uint32_t RlcCounterBlockNumCounters = 2;
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static const uint32_t SdmaCounterBlockNumCounters = 2;
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static const uint32_t UmcCounterBlockNumCounters = 5;
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static const uint32_t SpiCounterBlockNumCounters = 6;
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static const uint32_t SqCounterBlockNumCounters = 8;
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static const uint32_t SxCounterBlockNumCounters = 4;
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static const uint32_t TaCounterBlockNumCounters = 2;
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static const uint32_t TcaCounterBlockNumCounters = 4;
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static const uint32_t TccCounterBlockNumCounters = 4;
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static const uint32_t TcpCounterBlockNumCounters = 4;
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static const uint32_t TdCounterBlockNumCounters = 2;
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static const uint32_t VgtCounterBlockNumCounters = 4;
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static const uint32_t WdCounterBlockNumCounters = 4;
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static const uint32_t GceaCounterBlockNumCounters = 2;
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static const uint32_t AtcCounterBlockNumCounters = 4;
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static const uint32_t AtcL2CounterBlockNumCounters = 2;
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static const uint32_t McVmL2CounterBlockNumCounters = 8;
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static const uint32_t RpbCounterBlockNumCounters = 4;
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static const uint32_t RmiCounterBlockNumCounters = 4;
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static const uint32_t Gl1aCounterBlockNumCounters = 4;
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static const uint32_t Gl1cCounterBlockNumCounters = 4;
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static const uint32_t Gl2aCounterBlockNumCounters = 4;
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static const uint32_t Gl2cCounterBlockNumCounters = 4;
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static const uint32_t GcrCounterBlockNumCounters = 2;
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static const uint32_t GusCounterBlockNumCounters = 2;
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// Block counters max event value
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static const uint32_t CbCounterBlockMaxEvent =
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CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK; // CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD;
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static const uint32_t CpcCounterBlockMaxEvent = CPC_PERF_SEL_MEC_THREAD3;
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static const uint32_t CpfCounterBlockMaxEvent = CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY;
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static const uint32_t CpgCounterBlockMaxEvent = CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1;
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static const uint32_t DbCounterBlockMaxEvent = DB_PERF_SEL_OREO_Events_stalls;
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static const uint32_t GdsCounterBlockMaxEvent = GDS_PERF_SEL_SE7_GS_WAVE_ID_VALID;
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static const uint32_t GrbmCounterBlockMaxEvent = GRBM_PERF_SEL_CPAXI_BUSY;
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static const uint32_t GrbmSeCounterBlockMaxEvent = GRBM_PERF_SEL_CPAXI_BUSY;
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// static const uint32_t IaCounterBlockMaxEvent = ia_perf_utcl1_stall_utcl2_event;
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// static const uint32_t PaSuCounterBlockMaxEvent = PERF_CLIENT_UTCL1_INFLIGHT;
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static const uint32_t PaScCounterBlockMaxEvent =
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SC_SPI_WAVE_STALLED_BY_SPI; // SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND;
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static const uint32_t RlcCounterBlockMaxEvent = 7;
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static const uint32_t SdmaCounterBlockMaxEvent = 15; // SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER;
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static const uint32_t SpiCounterBlockMaxEvent = SPI_PERF_BUSY; // SC_SC_SPI_EVENT;
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static const uint32_t SqCounterBlockMaxEvent = SQ_PERF_SEL_NONE2; // SQC_PERF_SEL_DUMMY_LAST;
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static const uint32_t SxCounterBlockMaxEvent =
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SX_PERF_SEL_DB3_4X2_DISCARD; // SX_PERF_SEL_DB3_SIZE;
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// static const uint32_t TaCounterBlockMaxEvent = TA_PERF_SEL_first_xnack_on_phase3;
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// static const uint32_t TcaCounterBlockMaxEvent = TCA_PERF_SEL_CROSSBAR_STALL_TCC7;
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// static const uint32_t TccCounterBlockMaxEvent = TCC_PERF_SEL_CLIENT127_REQ;
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// static const uint32_t TcpCounterBlockMaxEvent = TCP_PERF_SEL_TCC_DCC_REQ;
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// static const uint32_t TdCounterBlockMaxEvent =
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// TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt; static const uint32_t VgtCounterBlockMaxEvent =
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// vgt_perf_sclk_te11_vld; static const uint32_t WdCounterBlockMaxEvent =
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// wd_perf_utcl1_stall_utcl2_event;
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static const uint32_t GceaCounterBlockMaxEvent = 76;
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static const uint32_t AtcCounterBlockMaxEvent = 23;
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static const uint32_t AtcL2CounterBlockMaxEvent = 7;
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static const uint32_t RpbCounterBlockMaxEvent = 62;
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static const uint32_t McVmL2CounterBlockMaxEvent = 20;
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static const uint32_t RmiCounterBlockMaxEvent =
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RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3; // RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3;
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static const uint32_t TcpCounterBlockMaxEvent = 61;
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static const uint32_t Gl1aCounterBlockMaxEvent = 24;
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static const uint32_t Gl1cCounterBlockMaxEvent = 84;
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static const uint32_t Gl2aCounterBlockMaxEvent = 108;
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static const uint32_t Gl2cCounterBlockMaxEvent = 259;
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static const uint32_t GcrCounterBlockMaxEvent = 155;
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static const uint32_t GusCounterBlockMaxEvent = 176;
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} // namespace gfx11
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} // namespace gfxip
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#endif // _GFX11_BLOCKINFO_H_
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