Evgeny
7c4369bde4
Contributors:
Ammar ELWazir <aelwazir@amd.com>
AravindanC <aravindan.cheruvally@amd.com>
Benjamin Welton <bewelton@amd.com>
Ma, Bing <Bing.Ma@amd.com>
Chun Yang <chun.yang@amd.com>
Cole Nelson <cole.nelson@amd.com>
Ethan Stewart <ethan.stewart@amd.com>
Evgeny <evgeny.shcherbakov@amd.com>
Freddy Paul <Freddy.paul@amd.com>
Giovanni Baraldi <gbaraldi@amd.com>
Gopesh Bhardwaj <Gopesh.Bhardwaj@amd.com>
Icarus Sparry <icarus.sparry@amd.com>
itrowbri <Ian.Trowbridge@amd.com>
James Edwards <JamesAdrian.Edwards@amd.com>
jatang <jatang@amd.com>
Jeremy Newton <Jeremy.Newton@amd.com>
Jonathan Kim <jonathan.kim@amd.com>
Kent Russell <kent.russell@amd.com>
Kiumars Sabeti <kiumars.sabeti@amd.com>
Lang Yu <lang.yu@amd.com>
Laurent Morichetti <laurent.morichetti@amd.com>
Mallya, Ameya Keshava <AmeyaKeshava.Mallya@amd.com>
Manjunath Jakaraddi <manjunath.jakaraddi@amd.com>
Mark Laws <markdavid.laws@amd.com>
Mohan Kumar Mithur <Mohan.KumarMithur@amd.com>
Nicholas Curtis <nicurtis@amd.com>
Nirmal Unnikrishnan <Nirmal.Unnikrishnan@amd.com>
Parag Bhandari <parag.bhandari@amd.com>
Ranjith Ramakrishnan <Ranjith.Ramakrishnan@amd.com>
Robert Gregory <Robert.Gregory@amd.com>
Saravanan Solaiyappan <saravanan.solaiyappan@amd.com>
Saurabh Verma <saurabh.verma@amd.com>
Srihari Uttanur <srihari.u@amd.com>
Srinivasan Subramanian <srinivasan.subramanian@amd.com>
Sriraksha Nagaraj <Sriraksha.Nagaraj@amd.com>
Sushma Vaddireddy <svaddire@amd.com>
Xianwei Zhang <Xianwei.Zhang@amd.com>
[ROCm/aqlprofile commit: 1ed169e30c]
286 linhas
12 KiB
C++
286 linhas
12 KiB
C++
// MIT License
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//
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// Copyright (c) 2017-2025 Advanced Micro Devices, Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#ifndef _GFX12_BLOCKINFO_H_
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#define _GFX12_BLOCKINFO_H_
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namespace gfxip {
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namespace gfx12 {
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#define __BLOCK_ID(block) HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_##block
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// Private PMC Counter BlockId is defined here
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// Pubclic PMC Counter BlockId is defined in hsa_ven_amd_aqlprofile.h
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enum CounterBlockId {
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__BLOCK_ID(RLC) = HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER,
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__BLOCK_ID(CPG),
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__BLOCK_ID(GRBMH),
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__BLOCK_ID(GRBMA),
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__BLOCK_ID(SQG),
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// mem blocks
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__BLOCK_ID(CHA),
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__BLOCK_ID(CHC),
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__BLOCK_ID(GLARBA),
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__BLOCK_ID(GLARBC),
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__BLOCK_ID(GC_CANE),
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__BLOCK_ID(GC_FFBM),
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__BLOCK_ID(GC_NHTTLB),
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__BLOCK_ID(GC_L2TLB),
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__BLOCK_ID(GC_UTCL1),
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__BLOCK_ID(GC_UTCL2),
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__BLOCK_ID(GC_VML2),
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__BLOCK_ID(GCEA_SE),
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// New SDMA Perfmon interface, comparing to the original SDMA PerfCnt. gfx12
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// supports both and they should provide the same counter events. We might
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// remove SDMA PerfCnt support in aqlprofile in the future since it is easier
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// to program Perfmon
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__BLOCK_ID(SDMA_PM),
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// Counters retrieved by KFD
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IommuV2CounterBlockId,
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KernelDriverCounterBlockId,
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CpPipeStatsCounterBlockId,
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HwInfoCounterBlockId,
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LastCounterBlockId = HwInfoCounterBlockId,
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};
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// Define SPM Counter BlockId
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enum SpmGlobalBlockId {
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SPM_GLOBAL_BLOCK_NAME_FIRST = 0,
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SPM_GLOBAL_BLOCK_NAME_CPG = SPM_GLOBAL_BLOCK_NAME_FIRST,
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SPM_GLOBAL_BLOCK_NAME_CPC,
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SPM_GLOBAL_BLOCK_NAME_CPF,
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SPM_GLOBAL_BLOCK_NAME_GDS,
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SPM_GLOBAL_BLOCK_NAME_GCR,
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SPM_GLOBAL_BLOCK_NAME_PH,
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SPM_GLOBAL_BLOCK_NAME_GE1,
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SPM_GLOBAL_BLOCK_NAME_GL2A,
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SPM_GLOBAL_BLOCK_NAME_GL2C,
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SPM_GLOBAL_BLOCK_NAME_SDMA,
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SPM_GLOBAL_BLOCK_NAME_GUS,
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SPM_GLOBAL_BLOCK_NAME_EA,
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SPM_GLOBAL_BLOCK_NAME_CHA,
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SPM_GLOBAL_BLOCK_NAME_CHC,
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SPM_GLOBAL_BLOCK_NAME_CHCG,
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SPM_GLOBAL_BLOCK_NAME_ATCL2,
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SPM_GLOBAL_BLOCK_NAME_VML2,
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SPM_GLOBAL_BLOCK_NAME_GE2_SE,
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SPM_GLOBAL_BLOCK_NAME_GE2_DIST,
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SPM_GLOBAL_BLOCK_NAME_FFBM,
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SPM_GLOBAL_BLOCK_NAME_CANE,
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SPM_GLOBAL_BLOCK_NAME_LAST = SPM_GLOBAL_BLOCK_NAME_CANE,
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};
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enum SpmSeBlockId {
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SPM_SE_BLOCK_NAME_FIRST = 0,
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SPM_SE_BLOCK_NAME_CB = SPM_SE_BLOCK_NAME_FIRST,
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SPM_SE_BLOCK_NAME_DB,
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SPM_SE_BLOCK_NAME_PA,
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SPM_SE_BLOCK_NAME_SX,
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SPM_SE_BLOCK_NAME_SC,
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SPM_SE_BLOCK_NAME_TA,
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SPM_SE_BLOCK_NAME_TD,
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SPM_SE_BLOCK_NAME_TCP,
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SPM_SE_BLOCK_NAME_SPI,
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SPM_SE_BLOCK_NAME_SQG,
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SPM_SE_BLOCK_NAME_GL1A,
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SPM_SE_BLOCK_NAME_RMI,
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SPM_SE_BLOCK_NAME_GL1C,
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SPM_SE_BLOCK_NAME_GL1CG,
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SPM_SE_BLOCK_NAME_CBR,
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SPM_SE_BLOCK_NAME_DBR,
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SPM_SE_BLOCK_NAME_GL1H,
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SPM_SE_BLOCK_NAME_SQC,
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SPM_SE_BLOCK_NAME_PC,
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SPM_SE_BLOCK_NAME_EA,
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SPM_SE_BLOCK_NAME_GE,
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SPM_SE_BLOCK_NAME_GL2A,
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SPM_SE_BLOCK_NAME_GL2C,
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SPM_SE_BLOCK_NAME_WGS,
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SPM_SE_BLOCK_NAME_GL1XA,
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SPM_SE_BLOCK_NAME_GL1XC,
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SPM_SE_BLOCK_NAME_UTCL1,
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SPM_SE_BLOCK_NAME_LAST = SPM_SE_BLOCK_NAME_UTCL1,
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};
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namespace gfx1201 {
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// IP versions for Radeon RX 9070
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// ip_block : gc_12_0_1
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// ip_block : athub_4_1_0
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// ip_block : umc_8_14_0
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// ip_block : df_4_15_1
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// ip_block : pcie_6_1_0
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// Number of block instances
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// Reference: global_features.h (from gfxip header file package)
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// rspm_config.pm (from design configuration files)
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// The following default values are generated from Radeon RX 9070, the first product of the
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// RDNA 4 lineup. It could change for other products, and the change will be made in
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// [PRODUCT_NAME]_factory.h
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//
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static const uint32_t GrbmCounterBlockNumInstances = 1;
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static const uint32_t RlcCounterBlockNumInstances = 1;
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static const uint32_t CpgCounterBlockNumInstances = 1;
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static const uint32_t CpcCounterBlockNumInstances = 1;
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static const uint32_t CpfCounterBlockNumInstances = 1;
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static const uint32_t GcrCounterBlockNumInstances = 1;
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static const uint32_t Ge1CounterBlockNumInstances = 1;
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static const uint32_t Gl2aCounterBlockNumInstances = 4; // GFX_CPWD__NUM_GL2A_PER_CPWD
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static const uint32_t Gl2cCounterBlockNumInstances = 32; // GFX_CPWD__NUM_GL2C_PER_CPWD
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static const uint32_t GceaCounterBlockNumInstances = 36; // GFX_CPWD__NUM_EA_PER_CPWD
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static const uint32_t ChaCounterBlockNumInstances = 1;
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static const uint32_t ChcCounterBlockNumInstances = 4; // GFX_CPWD__NUM_CHC
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static const uint32_t Ge2DistCounterBlockNumInstances = 1;
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static const uint32_t SdmaCounterBlockNumInstances = 2; // GFX_CPWD__NUM_SDMA_PER_CPWD
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static const uint32_t GcVml2CounterBlockNumInstances = 1;
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static const uint32_t GcMcVml2CounterBlockNumInstances = 1;
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static const uint32_t GcUtcl2CounterBlockNumInstances = 1;
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static const uint32_t GrbmhCounterBlockNumInstances = 1;
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static const uint32_t CbCounterBlockNumInstances = 2; // GFX_SE__NUM_RB_PER_SA
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static const uint32_t DbCounterBlockNumInstances = 2; // GFX_SE__NUM_RB_PER_SA
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static const uint32_t SuCounterBlockNumInstances = 1; // GFX_SE__NUM_PA_PER_SE
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static const uint32_t SxCounterBlockNumInstances = 1;
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static const uint32_t ScCounterBlockNumInstances = 2; // GFX_SE__NUM_PACKER_PER_SA
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static const uint32_t TaCounterBlockNumInstances = 2; // GFX_SE__NUM_ROWS_PER_WGP
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static const uint32_t TdCounterBlockNumInstances = 2; // GFX_SE__NUM_ROWS_PER_WGP
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static const uint32_t TcpCounterBlockNumInstances = 2; // GFX_SE__NUM_ROWS_PER_WGP
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static const uint32_t SpiCounterBlockNumInstances = 1;
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static const uint32_t SqgCounterBlockNumInstances = 1;
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static const uint32_t Gl1aCounterBlockNumInstances = 1;
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static const uint32_t RmiCounterBlockNumInstances = 2; // GFX_SE__NUM_RMI_PER_SA
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static const uint32_t Gl1cCounterBlockNumInstances = 4; // GFX_SE__NUM_GL1C_PER_SA
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static const uint32_t SqcCounterBlockNumInstances = 1;
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static const uint32_t PcCounterBlockNumInstances = 1;
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static const uint32_t GceaSeCounterBlockNumInstances = 4;
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static const uint32_t GeCounterBlockNumInstances = 1;
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static const uint32_t WgsCounterBlockNumInstances = 1;
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static const uint32_t Gl1xaCounterBlockNumInstances = 1;
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static const uint32_t Gl1xcCounterBlockNumInstances = 4; // GFX_SE__NUM_GL1C_PER_SA
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static const uint32_t GcUtcl1CounterBlockNumInstances = 2;
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static const uint32_t SdmaCounterBlockMaxInstances = 8;
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static const uint32_t UmcCounterBlockMaxInstances = 32;
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// Number of block counter registers - Auto-generated from chip_offset_byte.h, edit with extra
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// caution Reference: chip_offset_byte.h (from gfxip header file package) The following default
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// values are generated from Radeon RX 9070, the first product of the RDNA 4 lineup. It could change
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// for other products, and the change will be made in [PRODUCT_NAME]_factory.h
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//
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static const uint32_t GrbmCounterBlockNumCounters = 2;
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static const uint32_t RlcCounterBlockNumCounters = 2;
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static const uint32_t CpgCounterBlockNumCounters = 2;
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static const uint32_t CpcCounterBlockNumCounters = 2;
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static const uint32_t CpfCounterBlockNumCounters = 2;
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static const uint32_t GcrCounterBlockNumCounters = 2;
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static const uint32_t PhCounterBlockNumCounters = 8;
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static const uint32_t Ge1CounterBlockNumCounters = 4;
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static const uint32_t Gl2aCounterBlockNumCounters = 4;
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static const uint32_t Gl2cCounterBlockNumCounters = 4;
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static const uint32_t GceaCounterBlockNumCounters = 2;
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static const uint32_t ChaCounterBlockNumCounters = 4;
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static const uint32_t ChcCounterBlockNumCounters = 4;
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static const uint32_t Ge2DistCounterBlockNumCounters = 4;
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static const uint32_t SdmaCounterBlockNumCounters = 2;
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static const uint32_t GcVml2CounterBlockNumCounters = 2;
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static const uint32_t GcMcVml2CounterBlockNumCounters = 1;
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static const uint32_t GcUtcl2CounterBlockNumCounters = 1;
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static const uint32_t GrbmhCounterBlockNumCounters = 2;
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static const uint32_t CbCounterBlockNumCounters = 4;
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static const uint32_t DbCounterBlockNumCounters = 4;
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static const uint32_t SuCounterBlockNumCounters = 4;
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static const uint32_t SxCounterBlockNumCounters = 4;
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static const uint32_t PaScCounterBlockNumCounters = 8;
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static const uint32_t TaCounterBlockNumCounters = 2;
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static const uint32_t TdCounterBlockNumCounters = 2;
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static const uint32_t TcpCounterBlockNumCounters = 4;
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static const uint32_t SpiCounterBlockNumCounters = 6;
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static const uint32_t SqgCounterBlockNumCounters = 8;
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static const uint32_t Gl1aCounterBlockNumCounters = 4;
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static const uint32_t RmiCounterBlockNumCounters = 4;
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static const uint32_t Gl1cCounterBlockNumCounters = 4;
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static const uint32_t SqcCounterBlockNumCounters = 16;
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static const uint32_t PcCounterBlockNumCounters = 4;
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static const uint32_t GceaSeCounterBlockNumCounters = 2;
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static const uint32_t GeCounterBlockNumCounters = 4;
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static const uint32_t WgsCounterBlockNumCounters = 2;
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static const uint32_t Gl1xaCounterBlockNumCounters = 4;
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static const uint32_t Gl1xcCounterBlockNumCounters = 4;
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static const uint32_t GcUtcl1CounterBlockNumCounters = 4;
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// Block counters max event value - Auto-generated from chip_enum.h, edit with extra caution
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// Reference: chip_enum.h (from gfxip header file package)
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// The following default values are generated from Radeon RX 9070, the first product of the
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// RDNA 4 lineup. It could change for other products, and the change will be made in
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// [PRODUCT_NAME]_factory.h
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//
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static const uint32_t GrbmCounterBlockMaxEvent = 51;
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static const uint32_t RlcCounterBlockMaxEvent = 6;
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static const uint32_t CpgCounterBlockMaxEvent = 30;
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static const uint32_t CpcCounterBlockMaxEvent = 55;
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static const uint32_t CpfCounterBlockMaxEvent = 4;
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static const uint32_t GcrCounterBlockMaxEvent = 151;
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static const uint32_t PhCounterBlockMaxEvent = 1023;
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static const uint32_t Ge1CounterBlockMaxEvent = 54;
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static const uint32_t Gl2aCounterBlockMaxEvent = 114;
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static const uint32_t Gl2cCounterBlockMaxEvent = 249;
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static const uint32_t GceaCounterBlockMaxEvent = 32;
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static const uint32_t ChaCounterBlockMaxEvent = 25;
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static const uint32_t ChcCounterBlockMaxEvent = 94;
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static const uint32_t Ge2DistCounterBlockMaxEvent = 188;
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static const uint32_t SdmaCounterBlockMaxEvent = 125;
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static const uint32_t GcVml2CounterBlockMaxEvent = 90;
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static const uint32_t GcMcVml2CounterBlockMaxEvent =
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1; // This is handled by GCMC_VM_L2_PERFCOUNTER0_CFG
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static const uint32_t GcUtcl2CounterBlockMaxEvent = 36;
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static const uint32_t GrbmhCounterBlockMaxEvent = 25;
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static const uint32_t CbCounterBlockMaxEvent = 315;
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static const uint32_t DbCounterBlockMaxEvent = 441;
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static const uint32_t PaSuCounterBlockMaxEvent = 828;
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static const uint32_t SxCounterBlockMaxEvent = 81;
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static const uint32_t ScCounterBlockMaxEvent = 821;
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static const uint32_t TaCounterBlockMaxEvent = 254;
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static const uint32_t TdCounterBlockMaxEvent = 271;
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static const uint32_t TcpCounterBlockMaxEvent = 99;
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static const uint32_t SpiCounterBlockMaxEvent = 318;
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static const uint32_t SqgCounterBlockMaxEvent = 45;
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static const uint32_t Gl1aCounterBlockMaxEvent = 21;
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static const uint32_t RmiCounterBlockMaxEvent = 138;
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static const uint32_t Gl1cCounterBlockMaxEvent = 121;
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static const uint32_t SqcCounterBlockMaxEvent = 511;
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static const uint32_t PcCounterBlockMaxEvent = 164;
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static const uint32_t GceaSeCounterBlockMaxEvent = 32;
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static const uint32_t GeCounterBlockMaxEvent = 103;
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static const uint32_t WgsCounterBlockMaxEvent = 4;
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static const uint32_t Gl1xaCounterBlockMaxEvent = 21;
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static const uint32_t Gl1xcCounterBlockMaxEvent = 109;
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static const uint32_t GcUtcl1CounterBlockMaxEvent = 71;
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} // namespace gfx1201
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} // namespace gfx12
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} // namespace gfxip
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#endif // _GFX12_BLOCKINFO_H_
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