vedithal-amd
f9aa7be97c
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
1.5 KiB
1.5 KiB
| 1 | Dispatch_ID | GPU_ID | Queue_ID | PID | TID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Start_Timestamp | End_Timestamp | Correlation_ID | Kernel_ID | CPC_CPC_UTCL2IU_BUSY | CPC_SYNC_FIFO_FULL | SPI_CS0_NUM_THREADGROUPS | SPI_CS1_NUM_THREADGROUPS | SPI_CS2_NUM_THREADGROUPS | SPI_CS3_NUM_THREADGROUPS | SQC_DCACHE_REQ_READ_8 | SQC_TC_DATA_ATOMIC_REQ | SQ_ACTIVE_INST_VALU | SQ_BUSY_CYCLES | SQ_INSTS_SENDMSG | SQ_INSTS_VALU_ADD_F64 | SQ_LDS_BANK_CONFLICT | SQ_VMEM_TA_CMD_FIFO_FULL | TA_BUFFER_WAVEFRONTS_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | TCC_ALL_TC_OP_INV_EVICT_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | TCC_EA0_WRREQ_LEVEL_sum | TCC_UC_REQ_sum | TCP_TCC_READ_REQ_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1 | 15772 | 15772 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248227257271964 | 1248227257293723 | 1 | 13 | 389.0 | 0.0 | 4096.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 98304.0 | 126903.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 154249.0 | 0.0 | 36146.0 | 9826410.0 | 26.0 | 65536.0 | 11.0 | 768.0 | 0.0 |
| 3 | 1 | 0 | 1 | 15772 | 15772 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248227257962097 | 1248227257979016 | 2 | 13 | 0.0 | 0.0 | 4096.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 98304.0 | 96924.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 103050.0 | 0.0 | 36209.0 | 10285296.0 | 8.0 | 65536.0 | 0.0 | 0.0 | 0.0 |
| 4 | 2 | 0 | 1 | 15772 | 15772 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248227258551114 | 1248227258567914 | 3 | 13 | 0.0 | 0.0 | 4096.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 98304.0 | 96768.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 100616.0 | 0.0 | 36239.0 | 10281734.0 | 0.0 | 65536.0 | 0.0 | 0.0 | 0.0 |