Saurabh Verma
31a7f3d5dd
* Initial commit * Replaced gc_9_2_1_sh_mask.h with gc_9_4_2_sh_mask.h * properly replace gc_9_2_1_sh_mask.h and gc_9_2_1_offset.h for all gfx9 asics
816 lines
46 KiB
C++
816 lines
46 KiB
C++
// MIT License
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//
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// Copyright (c) 2017-2025 Advanced Micro Devices, Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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#ifndef _GFX9_BLOCKTABLE_H_
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#define _GFX9_BLOCKTABLE_H_
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namespace gfxip {
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namespace gfx9 {
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/*
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* The following tables contain register addresses of the SQ counter registers
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*/
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/*
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* SQ
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*/
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static const CounterRegInfo SqCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER9_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER9_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER9_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER11_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER11_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER11_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER13_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER13_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER13_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER15_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER15_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER15_HI), REG_32B_NULL}};
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/*
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* GRBM
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*/
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static const CounterRegInfo GrbmCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_HI), REG_32B_NULL}};
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/*
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* GRBM_SE
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*/
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static const CounterRegInfo GrbmSeCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_HI), REG_32B_NULL}};
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/*
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* PA_SU
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*/
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static const CounterRegInfo PaSuCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_SELECT1)},
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{REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* PA_SC
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*/
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static const CounterRegInfo PaScCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER3_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER4_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER4_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER5_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER5_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER6_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER6_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER7_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER7_HI), REG_32B_NULL}};
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/*
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* SPI
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*/
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static const CounterRegInfo SpiCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_SELECT1)},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_SELECT1)},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_SELECT1)},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_HI), REG_32B_NULL}};
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/*
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* TCA
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*/
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static const CounterRegInfo TcaCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_SELECT1)},
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{REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* TCC
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*/
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static const CounterRegInfo TccCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_SELECT1)},
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{REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* TCP
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*/
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static const CounterRegInfo TcpCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_SELECT1)},
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* CB
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*/
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static const CounterRegInfo CbCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* DB
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*/
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static const CounterRegInfo DbCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_SELECT1)},
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{REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* RLC
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*/
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static const CounterRegInfo RlcCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER1_HI), REG_32B_NULL}};
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/*
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* SX
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*/
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static const CounterRegInfo SxCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* TA
|
|
*/
|
|
static const CounterRegInfo TaCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* TD
|
|
*/
|
|
static const CounterRegInfo TdCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER1_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* GDS
|
|
*/
|
|
static const CounterRegInfo GdsCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* VGT
|
|
*/
|
|
static const CounterRegInfo VgtCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER2_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER3_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* IA
|
|
*/
|
|
static const CounterRegInfo IaCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER1_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER2_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER3_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* WD
|
|
*/
|
|
static const CounterRegInfo WdCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER0_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER1_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER2_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER3_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* CPC
|
|
*/
|
|
static const CounterRegInfo CpcCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* CPF
|
|
*/
|
|
static const CounterRegInfo CpfCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_HI), REG_32B_NULL}};
|
|
|
|
/*
|
|
* CPG
|
|
*/
|
|
static const CounterRegInfo CpgCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
|
REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER1_HI), REG_32B_NULL}};
|
|
|
|
// RMI
|
|
static const CounterRegInfo RmiCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL),
|
|
REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL),
|
|
REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER1_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL),
|
|
REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_SELECT1)},
|
|
{REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL),
|
|
REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER3_HI), REG_32B_NULL}};
|
|
|
|
// GCEA
|
|
static const CounterRegInfo GceaCounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER0_CFG),
|
|
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER1_CFG),
|
|
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL}};
|
|
|
|
// ATC
|
|
static const CounterRegInfo AtcCounterRegAddr[] = {
|
|
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER0_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER1_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER2_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER3_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL}};
|
|
|
|
// ATC L2
|
|
static const CounterRegInfo AtcL2CounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER0_CFG),
|
|
REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER1_CFG),
|
|
REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_HI), REG_32B_NULL}};
|
|
|
|
// RPB
|
|
static const CounterRegInfo RpbCounterRegAddr[] = {
|
|
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER0_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER1_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER2_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER3_CFG),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL}};
|
|
|
|
// MC VM L2
|
|
static const CounterRegInfo McVmL2CounterRegAddr[] = {
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER0_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER1_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER2_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER3_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER4_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER5_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER6_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
|
{REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER7_CFG),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO),
|
|
REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}};
|
|
|
|
// BlockDelayInfo for SPM
|
|
static const uint32_t SqBlockDelayValue[] = {0x3b, 0x38, 0x39, 0x36}; // Verified
|
|
static const uint32_t PaSuBlockDelayValue[] = {0x22, 0x22, 0x20, 0x20};
|
|
static const uint32_t PaScBlockDelayValue[] = {0x26, 0x26, 0x22, 0x22, 0x23, 0x23, 0x21, 0x21};
|
|
static const uint32_t SpiBlockDelayValue[] = {0x39, 0x39, 0x36, 0x36}; // Verified
|
|
static const uint32_t TcaBlockDelayValue[] = {0x18, 0x1c};
|
|
static const uint32_t TccBlockDelayValue[] = {
|
|
0x0f, 0x15, 0x17, 0x1d, 0x1b, 0x17, 0x13, 0x0f, 0x14, 0x18, 0x1c, 0x20, 0x1d, 0x19, 0x15, 0x11};
|
|
static const uint32_t TcpBlockDelayValue[] = {
|
|
0x30, 0x2e, 0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, // se0
|
|
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, // se1
|
|
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, // se2
|
|
0x2c, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, 0x0c}; // se3
|
|
static const uint32_t CbBlockDelayValue[] = {
|
|
0x1d, 0x08, 0x14, 0x11, 0x19, 0x04, 0x10, 0x0d, 0x19, 0x05, 0x11, 0x0e, 0x15, 0x00, 0x0c, 0x09};
|
|
static const uint32_t DbBlockDelayValue[] = {
|
|
0x1b, 0x0c, 0x17, 0x10, 0x17, 0x08, 0x13, 0x0c, 0x17, 0x09, 0x14, 0x0d, 0x13, 0x08, 0x0f, 0x08};
|
|
static const uint32_t SxBlockDelayValue[] = {0x06, 0x06, 0x08, 0x04};
|
|
static const uint32_t TaBlockDelayValue[] = {
|
|
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e,
|
|
0x28, 0x26, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b,
|
|
0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, 0x0c, 0x0a,
|
|
0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09};
|
|
static const uint32_t TdBlockDelayValue[] = {
|
|
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e,
|
|
0x28, 0x26, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b,
|
|
0x28, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b,
|
|
0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09};
|
|
static const uint32_t GdsBlockDelayValue[] = {0x2d};
|
|
static const uint32_t VgtBlockDelayValue[] = {0x27, 0x27, 0x23, 0x24};
|
|
static const uint32_t IaBlockDelayValue[] = {0x32};
|
|
static const uint32_t CpcBlockDelayValue[] = {0x3c};
|
|
static const uint32_t CpfBlockDelayValue[] = {0x32};
|
|
static const uint32_t CpgBlockDelayValue[] = {0x30}; // Verified
|
|
|
|
static const BlockDelayInfo SqBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), SqBlockDelayValue};
|
|
static const BlockDelayInfo PaSuBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_PA_PERFMON_SAMPLE_DELAY), PaSuBlockDelayValue};
|
|
static const BlockDelayInfo PaScBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SC_PERFMON_SAMPLE_DELAY), PaScBlockDelayValue};
|
|
static const BlockDelayInfo SpiBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), SpiBlockDelayValue};
|
|
static const BlockDelayInfo TcaBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY), TcaBlockDelayValue};
|
|
static const BlockDelayInfo TccBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), TccBlockDelayValue};
|
|
static const BlockDelayInfo TcpBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), TcpBlockDelayValue};
|
|
static const BlockDelayInfo CbBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CB_PERFMON_SAMPLE_DELAY), CbBlockDelayValue};
|
|
static const BlockDelayInfo DbBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_DB_PERFMON_SAMPLE_DELAY), DbBlockDelayValue};
|
|
static const BlockDelayInfo SxBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SX_PERFMON_SAMPLE_DELAY), SxBlockDelayValue};
|
|
static const BlockDelayInfo TaBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TA_PERFMON_SAMPLE_DELAY), TaBlockDelayValue};
|
|
static const BlockDelayInfo TdBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TD_PERFMON_SAMPLE_DELAY), TdBlockDelayValue};
|
|
static const BlockDelayInfo GdsBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY), GdsBlockDelayValue};
|
|
static const BlockDelayInfo VgtBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), VgtBlockDelayValue};
|
|
static const BlockDelayInfo IaBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_IA_PERFMON_SAMPLE_DELAY), IaBlockDelayValue};
|
|
static const BlockDelayInfo CpcBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY), CpcBlockDelayValue};
|
|
static const BlockDelayInfo CpfBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY), CpfBlockDelayValue};
|
|
static const BlockDelayInfo CpgBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY), CpgBlockDelayValue};
|
|
|
|
// Counter block info table
|
|
// SPM global blocks: CPG, CPC, CPF, GDS, TCC, TCA, IA, TCS
|
|
// SPM shader engine blocks: CB, DB, SC, SX, TA, TD, TCP, VGT, SQG, SPI, PA
|
|
// Counter block CB
|
|
static const GpuBlockInfo CbCounterBlockInfo = {"CB",
|
|
CbCounterBlockId,
|
|
CbCounterBlockNumInstances,
|
|
CbCounterBlockMaxEvent,
|
|
CbCounterBlockNumCounters,
|
|
CbCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_CB_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockCleanAttr,
|
|
CbBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_CB};
|
|
// Counter block DB
|
|
static const GpuBlockInfo DbCounterBlockInfo = {"DB",
|
|
DbCounterBlockId,
|
|
DbCounterBlockNumInstances,
|
|
DbCounterBlockMaxEvent,
|
|
DbCounterBlockNumCounters,
|
|
DbCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_DB_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockCleanAttr,
|
|
DbBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_DB};
|
|
// Counter block GRBM
|
|
static const GpuBlockInfo GrbmCounterBlockInfo = {
|
|
"GRBM",
|
|
GrbmCounterBlockId,
|
|
1,
|
|
GrbmCounterBlockMaxEvent,
|
|
GrbmCounterBlockNumCounters,
|
|
GrbmCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_GRBM_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockGRBMAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GRBMSE
|
|
static const GpuBlockInfo GrbmSeCounterBlockInfo = {
|
|
"GRBM_SE",
|
|
GrbmSeCounterBlockId,
|
|
1,
|
|
GrbmSeCounterBlockMaxEvent,
|
|
GrbmSeCounterBlockNumCounters,
|
|
GrbmSeCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_GRBM_SE0_PERFCOUNTER_SELECT,
|
|
CounterBlockDfltAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block PA_SU
|
|
static const GpuBlockInfo PaSuCounterBlockInfo = {
|
|
"PA_SU",
|
|
PaSuCounterBlockId,
|
|
1,
|
|
PaSuCounterBlockMaxEvent,
|
|
PaSuCounterBlockNumCounters,
|
|
PaSuCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_PA_SU_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr,
|
|
PaSuBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_PA};
|
|
// Counter block PA_SC
|
|
static const GpuBlockInfo PaScCounterBlockInfo = {
|
|
"PA_SC",
|
|
PaScCounterBlockId,
|
|
1,
|
|
PaScCounterBlockMaxEvent,
|
|
PaScCounterBlockNumCounters,
|
|
PaScCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_PA_SC_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr,
|
|
PaScBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_SC};
|
|
// Counter block SPI
|
|
static const GpuBlockInfo SpiCounterBlockInfo = {
|
|
"SPI",
|
|
SpiCounterBlockId,
|
|
1,
|
|
SpiCounterBlockMaxEvent,
|
|
SpiCounterBlockNumCounters,
|
|
SpiCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_SPI_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockSPIAttr,
|
|
SpiBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_SPI};
|
|
// Counter block SQ
|
|
static const GpuBlockInfo SqCounterBlockInfo = {"SQ",
|
|
SqCounterBlockId,
|
|
1,
|
|
SqCounterBlockMaxEvent,
|
|
SqCounterBlockNumCounters,
|
|
SqCounterRegAddr,
|
|
gfx9_cntx_prim::sq_select_value,
|
|
CounterBlockSeAttr | CounterBlockSqAttr,
|
|
SqBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_SQG};
|
|
static const GpuBlockInfo SqGsCounterBlockInfo = {"SQ_GS",
|
|
SqCounterBlockId,
|
|
1,
|
|
SqCounterBlockMaxEvent,
|
|
SqCounterBlockNumCounters,
|
|
SqCounterRegAddr,
|
|
gfx9_cntx_prim::sq_select_value,
|
|
CounterBlockSeAttr | CounterBlockSqAttr,
|
|
BLOCK_DELAY_NONE};
|
|
static const GpuBlockInfo SqVsCounterBlockInfo = {"SQ_VS",
|
|
SqCounterBlockId,
|
|
1,
|
|
SqCounterBlockMaxEvent,
|
|
SqCounterBlockNumCounters,
|
|
SqCounterRegAddr,
|
|
gfx9_cntx_prim::sq_select_value,
|
|
CounterBlockSeAttr | CounterBlockSqAttr,
|
|
BLOCK_DELAY_NONE};
|
|
static const GpuBlockInfo SqPsCounterBlockInfo = {"SQ_PS",
|
|
SqCounterBlockId,
|
|
1,
|
|
SqCounterBlockMaxEvent,
|
|
SqCounterBlockNumCounters,
|
|
SqCounterRegAddr,
|
|
gfx9_cntx_prim::sq_select_value,
|
|
CounterBlockSeAttr | CounterBlockSqAttr,
|
|
BLOCK_DELAY_NONE};
|
|
static const GpuBlockInfo SqHsCounterBlockInfo = {"SQ_HS",
|
|
SqCounterBlockId,
|
|
1,
|
|
SqCounterBlockMaxEvent,
|
|
SqCounterBlockNumCounters,
|
|
SqCounterRegAddr,
|
|
gfx9_cntx_prim::sq_select_value,
|
|
CounterBlockSeAttr | CounterBlockSqAttr,
|
|
BLOCK_DELAY_NONE};
|
|
static const GpuBlockInfo SqCsCounterBlockInfo = {"SQ_CS",
|
|
SqCounterBlockId,
|
|
1,
|
|
SqCounterBlockMaxEvent,
|
|
SqCounterBlockNumCounters,
|
|
SqCounterRegAddr,
|
|
gfx9_cntx_prim::sq_select_value,
|
|
CounterBlockSeAttr | CounterBlockSqAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block SX
|
|
static const GpuBlockInfo SxCounterBlockInfo = {"SX",
|
|
SxCounterBlockId,
|
|
1,
|
|
SxCounterBlockMaxEvent,
|
|
SxCounterBlockNumCounters,
|
|
SxCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_SX_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockCleanAttr,
|
|
SxBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_SX};
|
|
// Counter block TA
|
|
static const GpuBlockInfo TaCounterBlockInfo = {"TA",
|
|
TaCounterBlockId,
|
|
TaCounterBlockNumInstances,
|
|
TaCounterBlockMaxEvent,
|
|
TaCounterBlockNumCounters,
|
|
TaCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_TA_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockTcAttr,
|
|
TaBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_TA};
|
|
// Counter block TCA
|
|
static const GpuBlockInfo TcaCounterBlockInfo = {
|
|
"TCA",
|
|
TcaCounterBlockId,
|
|
TcaCounterBlockNumInstances,
|
|
TcaCounterBlockMaxEvent,
|
|
TcaCounterBlockNumCounters,
|
|
TcaCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_TCA_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockTcAttr | CounterBlockSpmGlobalAttr,
|
|
TcaBlockDelayInfo,
|
|
SPM_GLOBAL_BLOCK_NAME_TCA};
|
|
// Counter block TCC
|
|
static const GpuBlockInfo TccCounterBlockInfo = {
|
|
"TCC",
|
|
TccCounterBlockId,
|
|
TccCounterBlockNumInstances,
|
|
TccCounterBlockMaxEvent,
|
|
TccCounterBlockNumCounters,
|
|
TccCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_TCC_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockTcAttr | CounterBlockSpmGlobalAttr,
|
|
TccBlockDelayInfo,
|
|
SPM_GLOBAL_BLOCK_NAME_TCC};
|
|
// Counter block TD
|
|
static const GpuBlockInfo TdCounterBlockInfo = {"TD",
|
|
TdCounterBlockId,
|
|
TdCounterBlockNumInstances,
|
|
TdCounterBlockMaxEvent,
|
|
TdCounterBlockNumCounters,
|
|
TdCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_TD_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockTcAttr,
|
|
TdBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_TD};
|
|
// Counter block TCP
|
|
static const GpuBlockInfo TcpCounterBlockInfo = {
|
|
"TCP",
|
|
TcpCounterBlockId,
|
|
TcpCounterBlockNumInstances,
|
|
TcpCounterBlockMaxEvent,
|
|
TcpCounterBlockNumCounters,
|
|
TcpCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockTcAttr,
|
|
TcpBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_TCP};
|
|
// Counter block GDS
|
|
static const GpuBlockInfo GdsCounterBlockInfo = {
|
|
"GDS",
|
|
GdsCounterBlockId,
|
|
1,
|
|
GdsCounterBlockMaxEvent,
|
|
GdsCounterBlockNumCounters,
|
|
GdsCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_GDS_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
|
GdsBlockDelayInfo,
|
|
SPM_GLOBAL_BLOCK_NAME_GDS};
|
|
// Counter block VGT
|
|
static const GpuBlockInfo VgtCounterBlockInfo = {
|
|
"VGT",
|
|
VgtCounterBlockId,
|
|
1,
|
|
VgtCounterBlockMaxEvent,
|
|
VgtCounterBlockNumCounters,
|
|
VgtCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_VGT_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr,
|
|
VgtBlockDelayInfo,
|
|
SPM_SE_BLOCK_NAME_VGT};
|
|
// Counter block IA
|
|
static const GpuBlockInfo IaCounterBlockInfo = {"IA",
|
|
IaCounterBlockId,
|
|
1,
|
|
IaCounterBlockMaxEvent,
|
|
IaCounterBlockNumCounters,
|
|
IaCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_IA_PERFCOUNTER0_SELECT,
|
|
CounterBlockSeAttr | CounterBlockSpmGlobalAttr,
|
|
IaBlockDelayInfo,
|
|
SPM_GLOBAL_BLOCK_NAME_IA};
|
|
// Counter block WD
|
|
static const GpuBlockInfo WdCounterBlockInfo = {"WD",
|
|
WdCounterBlockId,
|
|
1,
|
|
WdCounterBlockMaxEvent,
|
|
WdCounterBlockNumCounters,
|
|
WdCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_WD_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block CPC
|
|
static const GpuBlockInfo CpcCounterBlockInfo = {
|
|
"CPC",
|
|
CpcCounterBlockId,
|
|
1,
|
|
CpcCounterBlockMaxEvent,
|
|
CpcCounterBlockNumCounters,
|
|
CpcCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_CPC_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
|
CpcBlockDelayInfo,
|
|
SPM_GLOBAL_BLOCK_NAME_CPC};
|
|
// Counter block CPF
|
|
static const GpuBlockInfo CpfCounterBlockInfo = {
|
|
"CPF",
|
|
CpfCounterBlockId,
|
|
1,
|
|
CpfCounterBlockMaxEvent,
|
|
CpfCounterBlockNumCounters,
|
|
CpfCounterRegAddr,
|
|
gfx9_cntx_prim::select_value_CPF_PERFCOUNTER0_SELECT,
|
|
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
|
CpfBlockDelayInfo,
|
|
SPM_GLOBAL_BLOCK_NAME_CPF};
|
|
// Counter block MCVM L2
|
|
static const GpuBlockInfo McVmL2CounterBlockInfo = {
|
|
"MCVML2",
|
|
McVmL2CounterBlockId,
|
|
1,
|
|
McVmL2CounterBlockMaxEvent,
|
|
McVmL2CounterBlockNumCounters,
|
|
McVmL2CounterRegAddr,
|
|
gfx9_cntx_prim::mc_select_value_MC_VM_L2_PERFCOUNTER0_CFG,
|
|
CounterBlockMcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block ATC L2
|
|
static const GpuBlockInfo AtcL2CounterBlockInfo = {
|
|
"ATCL2",
|
|
AtcL2CounterBlockId,
|
|
1,
|
|
AtcL2CounterBlockMaxEvent,
|
|
AtcL2CounterBlockNumCounters,
|
|
AtcL2CounterRegAddr,
|
|
gfx9_cntx_prim::mc_select_value_ATC_L2_PERFCOUNTER0_CFG,
|
|
CounterBlockMcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block ATC
|
|
static const GpuBlockInfo AtcCounterBlockInfo = {
|
|
"ATC",
|
|
AtcCounterBlockId,
|
|
1,
|
|
AtcCounterBlockMaxEvent,
|
|
AtcCounterBlockNumCounters,
|
|
AtcCounterRegAddr,
|
|
gfx9_cntx_prim::mc_select_value_ATC_PERFCOUNTER0_CFG,
|
|
CounterBlockAtcAttr | CounterBlockAidAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block GCEA
|
|
static const GpuBlockInfo GceaCounterBlockInfo = {
|
|
"GCEA",
|
|
GceaCounterBlockId,
|
|
GceaCounterBlockNumInstances,
|
|
GceaCounterBlockMaxEvent,
|
|
GceaCounterBlockNumCounters,
|
|
GceaCounterRegAddr,
|
|
gfx9_cntx_prim::mc_select_value_GCEA_PERFCOUNTER0_CFG,
|
|
CounterBlockMcAttr,
|
|
BLOCK_DELAY_NONE};
|
|
// Counter block RPB
|
|
static const GpuBlockInfo RpbCounterBlockInfo = {
|
|
"RPB",
|
|
RpbCounterBlockId,
|
|
1,
|
|
RpbCounterBlockMaxEvent,
|
|
RpbCounterBlockNumCounters,
|
|
RpbCounterRegAddr,
|
|
gfx9_cntx_prim::mc_select_value_RPB_PERFCOUNTER0_CFG,
|
|
CounterBlockRpbAttr | CounterBlockAidAttr,
|
|
BLOCK_DELAY_NONE};
|
|
|
|
} // namespace gfx9
|
|
} // namespace gfxip
|
|
|
|
#endif // _GFX9_BLOCKTABLE_H_
|