Jay Cornwall 94420e0624 Reserve 128 SGPRs per wave in context save area ...

Originally reserved 100 SGPRs per wave. Pre-gfx10 needs 102 SGPRs
and gfx10 needs 128 SGPRs. Reserve 128 SGPRs per wave for all ASICs
to simplify calculation.
Also double VGPR register size for gfx908 family

Change-Id: I98b741cbfa051f49ed37ff25d99f851f124be7b6
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>


[ROCm/ROCR-Runtime commit: 814e0f0bdc]

2019-08-22 23:33:26 -04:00

..

rocr-runtime

Reserve 128 SGPRs per wave in context save area

2019-08-22 23:33:26 -04:00