Longlong Yao
a2b449a370
Signed-off-by: Longlong Yao <Longlong.Yao@amd.com> Part-of: <http://10.67.69.192/wsl/libhsakmt/-/merge_requests/26>
246 lines
9.8 KiB
C++
246 lines
9.8 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _WSL_INC_WDDM_DEVICE_H_
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#define _WSL_INC_WDDM_DEVICE_H_
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#include <cassert>
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#include <ntstatus.h>
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#include <atomic>
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#include <memory>
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#include <vector>
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#include "inc/wddm/types.h"
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#include "inc/thunk_proxy/thunk_proxy.h"
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#include "inc/wddm/va_mgr.h"
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#include "inc/wddm/status.h"
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#include "inc/wddm/types.h"
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#include "inc/wddm/gpu_memory.h"
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#include "inc/wddm/cmd_util.h"
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namespace wsl {
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namespace thunk {
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//class Queue;
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class WDDMQueue;
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// WSL2 hyperv GPADL protocol limitation
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#define MAX_USERPTR_BLOCK_SIZE 0xf0000000
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class WDDMDevice {
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public:
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static constexpr size_t GpuMemoryChunkSize = 2 * (1ULL << 30); // 2 GB
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WDDMDevice(D3DKMT_HANDLE adapter, LUID adapter_luid);
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~WDDMDevice();
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int Major() { return device_info_.major; }
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int Minor() { return device_info_.minor; }
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int Stepping() { return device_info_.stepping; }
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bool IsDgpu() { return device_info_.is_dgpu; }
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const char *ProductName() { return device_info_.product_name; }
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const char *Uuid() { return device_info_.uuid; }
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thunk_proxy::AsicFamilyType GfxFamily() { return device_info_.family; }
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uint32_t DeviceId() { return device_info_.device_id; }
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uint32_t WavefrontSize() { return device_info_.wavefront_size; }
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uint32_t ComputeUnitCount() { return device_info_.compute_unit_count; }
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uint32_t MaxEngineClockMhz() { return device_info_.max_engine_clock_mhz; }
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uint32_t WatchPointsNum() { return device_info_.watch_points_num; }
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uint32_t PciBusAddr() { return device_info_.pci_bus_addr; }
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uint32_t MemoryBusWidth() { return device_info_.memory_bus_width; }
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uint32_t MaxMemoryClockMhz() { return device_info_.max_memory_clock_mhz; }
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uint32_t WavePerCu() { return device_info_.wave_per_cu; }
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uint32_t SimdPerCu() { return device_info_.simd_per_cu; }
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uint32_t MaxScratchSlotsPerCu() { return device_info_.max_scratch_slots_per_cu; }
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uint32_t NumShaderEngine() { return device_info_.num_shader_engine; }
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uint32_t ShaderArrayPerShaderEngine() { return device_info_.shader_array_per_shader_engine; }
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uint32_t NumSdmaEngine() { return device_info_.sdma_schedid.size(); }
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uint32_t Domain() { return device_info_.domain; }
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uint32_t NumGws() { return device_info_.num_gws; }
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uint32_t AsicRevision() { return device_info_.asic_revision; }
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uint64_t LocalHeapSize() { return device_info_.local_visible_heap_size + device_info_.local_invisible_heap_size; }
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uint64_t LocalVisibleHeapSize() { return device_info_.local_visible_heap_size; }
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uint64_t LocalInvisibleHeapSize() { return device_info_.local_invisible_heap_size; }
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uint64_t PrivateApertureBase() { return device_info_.private_aperture_base; }
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uint64_t PrivateApertureSize() { return device_info_.private_aperture_size; }
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uint64_t SharedApertureBase() { return device_info_.shared_aperture_base; }
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uint64_t SharedApertureSize() { return device_info_.shared_aperture_size; }
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uint32_t LdsSize() { return device_info_.lds_size; }
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uint64_t GPUCounterFrequency() { return device_info_.gpu_counter_frequency; }
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uint32_t GetSwsQueueSize(void) const { return device_info_.user_queue_size; }
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uint32_t GetMecFwVersion() { return device_info_.mec_fw_version; }
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uint32_t GetSdmaFwVersion() { return device_info_.sdma_fw_version; }
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uint32_t GetL1CacheSize() { return device_info_.l1_cache_size; }
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uint32_t GetL2CacheSize() { return device_info_.l2_cache_size; }
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uint32_t GetL3CacheSize() { return device_info_.l3_cache_size; }
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uint32_t Gl2CacheLineSize() { return device_info_.gl2_cacheline_size; }
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bool SupportStateShadowingByCpFw(void) const { return device_info_.state_shadowing_by_cpfw; }
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bool SupportPlatformAtomic(void) const { return device_info_.platform_atomic_support; }
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uint32_t GetSdmaEngine(uint32_t idx) {
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assert(idx < NumSdmaEngine());
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return device_info_.sdma_schedid[idx];
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}
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uint32_t GetComputeEngine() { return device_info_.compute_schedid; }
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uint64_t VramAvail();
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void GetClockCounters(uint64_t *gpu, uint64_t *cpu);
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uint32_t GetNumCpQueues() { return device_info_.num_cp_queues; }
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bool CreateSyncobj(D3DKMT_HANDLE *handle, uint64_t **addr);
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void DestroySyncobj(D3DKMT_HANDLE handle);
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bool CreateQueue(WDDMQueue *queue);
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void DestroyQueue(WDDMQueue *queue);
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bool CreateHwQueue(WDDMQueue *queue);
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bool DestroyHwQueue(WDDMQueue *queue);
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bool SubmitToSwQueue(WDDMQueue *queue, uint64_t command_addr,
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uint64_t command_size, uint64_t fence_value);
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bool SubmitToHwQueue(WDDMQueue *queue, uint64_t command_addr,
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uint64_t command_size, uint64_t fence_value);
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bool WaitPagingFence(WDDMQueue *queue) {
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uint64_t value = page_fence_value_;
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if (*page_fence_addr_ < value &&
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!GpuWait(queue, &page_syncobj_, &value, 1))
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return false;
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return true;
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}
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bool GpuWait(WDDMQueue *queue, const D3DKMT_HANDLE *syncobjs,
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uint64_t *values, int count);
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bool GpuSignal(D3DKMT_HANDLE context, const D3DKMT_HANDLE *syncobjs,
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uint64_t *value, int count);
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bool CpuWait(const D3DKMT_HANDLE *syncobjs, uint64_t *value,
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int count, bool wait_any);
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bool WaitOnPagingFenceFromCpu();
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uint32_t LdsBlocks(const hsa_kernel_dispatch_packet_t *pkt);
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uint32_t GetCmdbufSize(void) const { return cmdbuf_size_; }
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uint32_t GetAqlFrameSize(void) const { return cmdbuf_aql_frame_size_; }
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static uint32_t GetAqlFrameNum(void) { return cmdbuf_aql_frame_num_; }
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// Both legacy HWS and stage 1 HWS use KMD to alloc use queue memory,
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// return false by default
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bool AllocUserQueueMemFromUMD(void) const { return false; }
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bool IsHwsEnabled(int engine) {
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return thunk_proxy::GetHwsEnabled(engine, &device_info_);
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}
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void UpdatePageFence(uint64_t fence_value);
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D3DKMT_HANDLE PagingQueue() const { return page_queue_; }
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D3DKMT_HANDLE PagingFence() const { return page_syncobj_; }
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D3DKMT_HANDLE DeviceHandle() const { return device_; }
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LUID GetLuid() const { return adapter_luid_; }
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const thunk_proxy::DeviceInfo& DeviceInfo() const { return device_info_; }
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ErrorCode ReserveGpuVirtualAddress(thunk_proxy::AllocDomain domain,
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gpusize hit_base_addr,
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gpusize size,
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gpusize *out_gpu_virtual_addr,
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gpusize alignment,
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bool lock=false);
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ErrorCode FreeGpuVirtualAddress(thunk_proxy::AllocDomain domain,
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gpusize base_addr,
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gpusize size);
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ErrorCode CreateGpuMemory(const GpuMemoryCreateInfo &create_info, GpuMemory **gpu_mem);
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private:
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bool ParseDeviceInfo(void);
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void DestroyDeviceInfo(void);
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bool CreateDevice(void);
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bool DestroyDevice(void);
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bool CreatePagingQueue(void);
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bool DestroyPagingQueue(void);
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void *Lock(D3DKMT_HANDLE handle);
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bool Unlock(D3DKMT_HANDLE handle);
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bool CreateContext(int engine, D3DKMT_HANDLE *handle);
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bool DestroyContext(D3DKMT_HANDLE handle);
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void SetPowerOptimization(bool restore);
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void InitCmdbufInfo(void);
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bool ReserveSystemHeapSpace(void);
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bool FreeSystemHeapSpace(void);
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bool ReserveLocalHeapSpace(void);
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bool CommitSystemHeapSpace(void* addr, int64_t size, bool lock=false);
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bool DecommitSystemHeapSpace(void* addr, int64_t size);
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bool FreeLocalHeapSpace(void);
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void InitVaMgr();
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D3DKMT_HANDLE adapter_;
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LUID adapter_luid_;
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D3DKMT_HANDLE device_;
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D3DKMT_HANDLE page_queue_;
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D3DKMT_HANDLE page_syncobj_;
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uint64_t *page_fence_addr_;
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std::atomic<uint64_t> page_fence_value_;
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uint64_t local_heap_space_start_;
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uint64_t local_heap_space_size_;
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uint64_t system_heap_space_start_;
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uint64_t system_heap_space_size_;
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uint32_t cmdbuf_size_;
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uint32_t cmdbuf_aql_frame_size_;
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static const uint32_t cmdbuf_aql_frame_num_;
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// device info
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thunk_proxy::DeviceInfo device_info_;
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std::unique_ptr<VaMgr> local_va_mgr_;
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//CmdUtil cmd_util;
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};
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NTSTATUS WDDMGetAdapters(D3DKMT_ADAPTERINFO *&adapters, int &num_adapters);
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} // namespace thunk
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} // namespace wsl
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#endif
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