James Edwards (xN/A) TX
7d2bc9d113
[git-p4: depot-paths = "//depot/stg/hsa/drivers/hsa/runtime/": change = 1250152]
296 lignes
11 KiB
C
296 lignes
11 KiB
C
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef AMD_HSA_ELF_H
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#define AMD_HSA_ELF_H
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#include "amd_hsa_common.h"
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// ELF Header Enumeration Values.
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#define EM_AMDGPU 224
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#define ELFOSABI_AMDGPU_HSA 64
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#define ELFABIVERSION_AMDGPU_HSA 0
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#define EF_AMDGPU_XNACK 0x00000001
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#define EF_AMDGPU_TRAP_HANDLER 0x00000002
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// ELF Section Header Flag Enumeration Values.
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#define SHF_AMDGPU_HSA_GLOBAL (0x00100000 & SHF_MASKOS)
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#define SHF_AMDGPU_HSA_READONLY (0x00200000 & SHF_MASKOS)
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#define SHF_AMDGPU_HSA_CODE (0x00400000 & SHF_MASKOS)
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#define SHF_AMDGPU_HSA_AGENT (0x00800000 & SHF_MASKOS)
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//
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typedef enum {
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AMDGPU_HSA_SEGMENT_GLOBAL_PROGRAM = 0,
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AMDGPU_HSA_SEGMENT_GLOBAL_AGENT = 1,
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AMDGPU_HSA_SEGMENT_READONLY_AGENT = 2,
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AMDGPU_HSA_SEGMENT_CODE_AGENT = 3,
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AMDGPU_HSA_SEGMENT_LAST,
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} amdgpu_hsa_elf_segment_t;
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// ELF Program Header Type Enumeration Values.
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#define PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM (PT_LOOS + AMDGPU_HSA_SEGMENT_GLOBAL_PROGRAM)
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#define PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_GLOBAL_AGENT)
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#define PT_AMDGPU_HSA_LOAD_READONLY_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_READONLY_AGENT)
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#define PT_AMDGPU_HSA_LOAD_CODE_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_CODE_AGENT)
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// ELF Symbol Type Enumeration Values.
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#define STT_AMDGPU_HSA_KERNEL (STT_LOOS + 0)
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#define STT_AMDGPU_HSA_INDIRECT_FUNCTION (STT_LOOS + 1)
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#define STT_AMDGPU_HSA_METADATA (STT_LOOS + 2)
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// ELF Symbol Binding Enumeration Values.
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#define STB_AMDGPU_HSA_EXTERNAL (STB_LOOS + 0)
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// ELF Symbol Other Information Creation/Retrieval.
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#define ELF64_ST_AMDGPU_ALLOCATION(o) (((o) >> 2) & 0x3)
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#define ELF64_ST_AMDGPU_FLAGS(o) ((o) >> 4)
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#define ELF64_ST_AMDGPU_OTHER(f, a, v) (((f) << 4) + (((a) & 0x3) << 2) + ((v) & 0x3))
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typedef enum {
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AMDGPU_HSA_SYMBOL_ALLOCATION_DEFAULT = 0,
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AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_PROGRAM = 1,
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AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_AGENT = 2,
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AMDGPU_HSA_SYMBOL_ALLOCATION_READONLY_AGENT = 3,
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AMDGPU_HSA_SYMBOL_ALLOCATION_LAST,
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} amdgpu_hsa_symbol_allocation_t;
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// ELF Symbol Allocation Enumeration Values.
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#define STA_AMDGPU_HSA_DEFAULT AMDGPU_HSA_SYMBOL_ALLOCATION_DEFAULT
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#define STA_AMDGPU_HSA_GLOBAL_PROGRAM AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_PROGRAM
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#define STA_AMDGPU_HSA_GLOBAL_AGENT AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_AGENT
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#define STA_AMDGPU_HSA_READONLY_AGENT AMDGPU_HSA_SYMBOL_ALLOCATION_READONLY_AGENT
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typedef enum {
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AMDGPU_HSA_SYMBOL_FLAG_DEFAULT = 0,
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AMDGPU_HSA_SYMBOL_FLAG_CONST = 1,
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AMDGPU_HSA_SYMBOL_FLAG_LAST,
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} amdgpu_hsa_symbol_flag_t;
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// ELF Symbol Flag Enumeration Values.
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#define STF_AMDGPU_HSA_CONST AMDGPU_HSA_SYMBOL_FLAG_CONST
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// AMD GPU Relocation Type Enumeration Values.
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#define R_AMDGPU_NONE 0
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#define R_AMDGPU_32_LOW 1
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#define R_AMDGPU_32_HIGH 2
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#define R_AMDGPU_64 3
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#define R_AMDGPU_INIT_SAMPLER 4
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#define R_AMDGPU_INIT_IMAGE 5
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// AMD GPU Note Type Enumeration Values.
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#define NT_AMDGPU_HSA_CODE_OBJECT_VERSION 1
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#define NT_AMDGPU_HSA_HSAIL 2
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#define NT_AMDGPU_HSA_ISA 3
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#define NT_AMDGPU_HSA_PRODUCER 4
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#define NT_AMDGPU_HSA_PRODUCER_OPTIONS 5
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#define NT_AMDGPU_HSA_EXTENSION 6
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#define NT_AMDGPU_HSA_HLDEBUG_DEBUG 101
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#define NT_AMDGPU_HSA_HLDEBUG_TARGET 102
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// AMD GPU Metadata Kind Enumeration Values.
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typedef uint16_t amdgpu_hsa_metadata_kind16_t;
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typedef enum {
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AMDGPU_HSA_METADATA_KIND_NONE = 0,
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AMDGPU_HSA_METADATA_KIND_INIT_SAMP = 1,
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AMDGPU_HSA_METADATA_KIND_INIT_ROIMG = 2,
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AMDGPU_HSA_METADATA_KIND_INIT_WOIMG = 3,
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AMDGPU_HSA_METADATA_KIND_INIT_RWIMG = 4
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} amdgpu_hsa_metadata_kind_t;
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// AMD GPU Sampler Coordinate Normalization Enumeration Values.
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typedef uint8_t amdgpu_hsa_sampler_coord8_t;
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typedef enum {
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AMDGPU_HSA_SAMPLER_COORD_UNNORMALIZED = 0,
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AMDGPU_HSA_SAMPLER_COORD_NORMALIZED = 1
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} amdgpu_hsa_sampler_coord_t;
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// AMD GPU Sampler Filter Enumeration Values.
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typedef uint8_t amdgpu_hsa_sampler_filter8_t;
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typedef enum {
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AMDGPU_HSA_SAMPLER_FILTER_NEAREST = 0,
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AMDGPU_HSA_SAMPLER_FILTER_LINEAR = 1
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} amdgpu_hsa_sampler_filter_t;
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// AMD GPU Sampler Addressing Enumeration Values.
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typedef uint8_t amdgpu_hsa_sampler_addressing8_t;
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typedef enum {
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AMDGPU_HSA_SAMPLER_ADDRESSING_UNDEFINED = 0,
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AMDGPU_HSA_SAMPLER_ADDRESSING_CLAMP_TO_EDGE = 1,
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AMDGPU_HSA_SAMPLER_ADDRESSING_CLAMP_TO_BORDER = 2,
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AMDGPU_HSA_SAMPLER_ADDRESSING_REPEAT = 3,
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AMDGPU_HSA_SAMPLER_ADDRESSING_MIRRORED_REPEAT = 4
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} amdgpu_hsa_sampler_addressing_t;
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// AMD GPU Sampler Descriptor.
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typedef struct amdgpu_hsa_sampler_descriptor_s {
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uint16_t size;
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amdgpu_hsa_metadata_kind16_t kind;
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amdgpu_hsa_sampler_coord8_t coord;
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amdgpu_hsa_sampler_filter8_t filter;
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amdgpu_hsa_sampler_addressing8_t addressing;
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uint8_t reserved1;
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} amdgpu_hsa_sampler_descriptor_t;
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// AMD GPU Image Geometry Enumeration Values.
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typedef uint8_t amdgpu_hsa_image_geometry8_t;
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typedef enum {
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AMDGPU_HSA_IMAGE_GEOMETRY_1D = 0,
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AMDGPU_HSA_IMAGE_GEOMETRY_2D = 1,
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AMDGPU_HSA_IMAGE_GEOMETRY_3D = 2,
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AMDGPU_HSA_IMAGE_GEOMETRY_1DA = 3,
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AMDGPU_HSA_IMAGE_GEOMETRY_2DA = 4,
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AMDGPU_HSA_IMAGE_GEOMETRY_1DB = 5,
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AMDGPU_HSA_IMAGE_GEOMETRY_2DDEPTH = 6,
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AMDGPU_HSA_IMAGE_GEOMETRY_2DADEPTH = 7
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} amdgpu_hsa_image_geometry_t;
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// AMD GPU Image Channel Order Enumeration Values.
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typedef uint8_t amdgpu_hsa_image_channel_order8_t;
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typedef enum {
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_A = 0,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_R = 1,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RX = 2,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RG = 3,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGX = 4,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RA = 5,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGB = 6,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGBX = 7,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGBA = 8,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_BGRA = 9,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_ARGB = 10,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_ABGR = 11,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGB = 12,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGBX = 13,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGBA = 14,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SBGRA = 15,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_INTENSITY = 16,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_LUMINANCE = 17,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_DEPTH = 18,
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AMDGPU_HSA_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL = 19
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} amdgpu_hsa_image_channel_order_t;
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// AMD GPU Image Channel Type Enumeration Values.
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typedef uint8_t amdgpu_hsa_image_channel_type8_t;
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typedef enum {
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SNORM_INT8 = 0,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SNORM_INT16 = 1,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT8 = 2,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT16 = 3,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT24 = 4,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SHORT_555 = 5,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SHORT_565 = 6,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_INT_101010 = 7,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT8 = 8,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT16 = 9,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT32 = 10,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8 = 11,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16 = 12,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32 = 13,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_HALF_FLOAT = 14,
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AMDGPU_HSA_IMAGE_CHANNEL_TYPE_FLOAT = 15
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} amdgpu_hsa_image_channel_type_t;
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// AMD GPU Image Descriptor.
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typedef struct amdgpu_hsa_image_descriptor_s {
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uint16_t size;
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amdgpu_hsa_metadata_kind16_t kind;
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amdgpu_hsa_image_geometry8_t geometry;
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amdgpu_hsa_image_channel_order8_t channel_order;
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amdgpu_hsa_image_channel_type8_t channel_type;
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uint8_t reserved1;
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uint64_t width;
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uint64_t height;
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uint64_t depth;
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uint64_t array;
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} amdgpu_hsa_image_descriptor_t;
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typedef struct amdgpu_hsa_note_code_object_version_s {
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uint32_t major_version;
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uint32_t minor_version;
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} amdgpu_hsa_note_code_object_version_t;
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typedef struct amdgpu_hsa_note_hsail_s {
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uint32_t hsail_major_version;
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uint32_t hsail_minor_version;
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uint8_t profile;
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uint8_t machine_model;
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uint8_t default_float_round;
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} amdgpu_hsa_note_hsail_t;
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typedef struct amdgpu_hsa_note_isa_s {
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uint16_t vendor_name_size;
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uint16_t architecture_name_size;
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uint32_t major;
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uint32_t minor;
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uint32_t stepping;
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char vendor_and_architecture_name[1];
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} amdgpu_hsa_note_isa_t;
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typedef struct amdgpu_hsa_note_producer_s {
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uint16_t producer_name_size;
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uint16_t reserved;
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uint32_t producer_major_version;
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uint32_t producer_minor_version;
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char producer_name[1];
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} amdgpu_hsa_note_producer_t;
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typedef struct amdgpu_hsa_note_producer_options_s {
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uint16_t producer_options_size;
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char producer_options[1];
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} amdgpu_hsa_note_producer_options_t;
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typedef enum {
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AMDGPU_HSA_RODATA_GLOBAL_PROGRAM = 0,
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AMDGPU_HSA_RODATA_GLOBAL_AGENT,
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AMDGPU_HSA_RODATA_READONLY_AGENT,
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AMDGPU_HSA_DATA_GLOBAL_PROGRAM,
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AMDGPU_HSA_DATA_GLOBAL_AGENT,
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AMDGPU_HSA_DATA_READONLY_AGENT,
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AMDGPU_HSA_BSS_GLOBAL_PROGRAM,
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AMDGPU_HSA_BSS_GLOBAL_AGENT,
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AMDGPU_HSA_BSS_READONLY_AGENT,
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AMDGPU_HSA_SECTION_LAST,
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} amdgpu_hsa_elf_section_t;
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#endif // AMD_HSA_ELF_H
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