JoseSantosAMD
da506ad9b5
* Updated links in documentation. (#328) Updated to reflect new GitHub organization. Fixed broken links to GitHub pages. Signed-off-by: David Galiffi <David.Galiffi@amd.com> * update branch for 2.x documentation builds Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * update checkout action and use concurrency instead of cancel-workflow-action Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * test addition of user option for container launch Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * remove --user option for container, try chown instead Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * fixing yaml syntax Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * reorder job step - start with checkout Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * restore missing run directive Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * Update workloads to include log.txt Add missing MI200 workloads Signed-off-by: Jose Santos <josantos@amd.com> * Signed-off-by: Jose Santos <josantos@amd.com> Add vcopy workload for tests * Change exit codes for caught failures Signed-off-by: Jose Santos <josantos@amd.com> * reformat Signed-off-by: Jose Santos <josantos@amd.com> * Add pytest-xdist for pytest -n Signed-off-by: Jose Santos <josantos@amd.com> --------- Signed-off-by: David Galiffi <David.Galiffi@amd.com> Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> Signed-off-by: Jose Santos <josantos@amd.com> Co-authored-by: David Galiffi <David.Galiffi@amd.com> Co-authored-by: Karl W. Schulz <karl.schulz@amd.com>
30 KiB
30 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_DRAM_sum | TCC_TAG_STALL_sum | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | wave_size_1 | obj_1 | SQ_INSTS_VALU_MUL_F32 | SQ_INSTS_VALU_FMA_F32 | SQ_INSTS_VALU_TRANS_F32 | SQ_INSTS_VALU_ADD_F64 | SQ_INSTS_VALU_MUL_F64 | SQ_INSTS_VALU_FMA_F64 | SQ_INSTS_VALU_TRANS_F64 | SQ_INSTS_VALU_INT32 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_2 | obj_2 | SQ_INSTS_SMEM_NORM | SQ_INSTS_MFMA | SQ_INSTS_VALU_MFMA_I8 | SQ_INSTS_VALU_MFMA_F16 | SQ_INSTS_VALU_MFMA_BF16 | SQ_INSTS_VALU_MFMA_F32 | SQ_INSTS_VALU_MFMA_F64 | SQ_VALU_MFMA_BUSY_CYCLES | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | TCC_EA_ATOMIC_LEVEL_sum | wave_size_3 | obj_3 | SQ_INSTS_VSKIPPED | SQ_INSTS | SQ_INSTS_VALU | SQ_INSTS_VALU_ADD_F16 | SQ_INSTS_VALU_MUL_F16 | SQ_INSTS_VALU_FMA_F16 | SQ_INSTS_VALU_TRANS_F16 | SQ_INSTS_VALU_ADD_F32 | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_SPI_STALL_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_4 | obj_4 | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_5 | obj_5 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_6 | obj_6 | SQ_WAVE_CYCLES | SQ_WAIT_ANY | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_BUSY_CU_CYCLES | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_7 | obj_7 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | wave_size_8 | obj_8 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_9 | obj_9 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_10 | obj_10 | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | wave_size_11 | obj_11 | SQC_TC_DATA_WRITE_REQ | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | wave_size_12 | obj_12 | SQ_INSTS_VALU_INT64 | SQ_INSTS_SMEM | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | TD_COALESCABLE_WAVEFRONT_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_13 | obj_13 | SQC_ICACHE_MISSES_DUPLICATE | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | wave_size_14 | obj_14 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_15 | obj_15 | SQC_DCACHE_REQ_READ_1 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | wave_size_16 | obj_16 | SQ_INSTS_FLAT_LDS_ONLY | SQ_INSTS_VALU_MFMA_MOPS_I8 | SQ_INSTS_VALU_MFMA_MOPS_F16 | SQ_INSTS_VALU_MFMA_MOPS_BF16 | SQ_INSTS_VALU_MFMA_MOPS_F32 | SQ_INSTS_VALU_MFMA_MOPS_F64 | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | wave_size_17 | obj_17 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_WAVES | SQ_INSTS_VALU_CVT | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_18 | obj_18 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f1570dbcec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131081.0 | 34758.0 | 45976.0 | 19560.0 | 64 | 0x7fdc1db54ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 13444 | 19343 | 8358 | 545 | 0 | 27202 | 204502.0 | 0.0 | 73417.0 | 131085.0 | 64 | 0x7f931b1e8ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 39359692.0 | 35836456.0 | 0.0 | 64 | 0x7f523a854ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 18303 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 393.0 | 32768.0 | 4096 | 16384 | 352 | 28428 | 1946 | 0 | 56.0 | 7.0 | 0.0 | 204031.0 | 64 | 0x7f3a11414ec0 | 0 | 1448230 | 4096 | 4096 | 0 | 1320647 | 4096 | 4096 | 0 | 1327106 | 4096 | 4096 | 0 | 1165103 | 4096 | 4096 | 0 | 1440333 | 4096 | 4096 | 0 | 1509519 | 4096 | 4096 | 0 | 1259467 | 4096 | 4096 | 0 | 1260905 | 4096 | 4096 | 0 | 1053199 | 4096 | 4096 | 0 | 1052202 | 4096 | 4096 | 0 | 1161616 | 4096 | 4096 | 0 | 1177706 | 4096 | 4096 | 0 | 1232425 | 4096 | 4096 | 0 | 1577487 | 4096 | 4096 | 0 | 1310715 | 4096 | 4096 | 0 | 1276195 | 4096 | 4096 | 0 | 944910 | 4096 | 4096 | 0 | 1170562 | 4096 | 4096 | 0 | 1325109 | 4096 | 4096 | 0 | 1476059 | 4096 | 4096 | 0 | 1220805 | 4096 | 4096 | 0 | 1491154 | 4100 | 4100 | 0 | 1255702 | 4096 | 4096 | 0 | 1301539 | 4096 | 4096 | 0 | 1343866 | 4096 | 4096 | 0 | 1120128 | 4096 | 4096 | 0 | 1061607 | 4096 | 4096 | 0 | 1371499 | 4096 | 4096 | 0 | 1128497 | 4096 | 4096 | 0 | 1092113 | 4096 | 4096 | 0 | 1117188 | 4096 | 4096 | 0 | 1555474 | 4096 | 4096 | 64 | 0x7f89343bcec0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4098 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 11 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 3 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 49 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 64 | 0x7f083fe4cec0 | 11146317 | 9870223 | 932030 | 344064 | 1655709 | 0 | 0 | 163840 | 832.0 | 515149.0 | 0.0 | 524288.0 | 262474.0 | 32768.0 | 528709 | 0 | 0 | 11222 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7f8503d18ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65551.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f53cdd50ec0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 0 | 27842 | 0 | 0 | 64 | 0x7f3893ad8ec0 | 2266 | 4096 | 2266 | 6362 | 2304 | 4096 | 2304 | 6400 | 2299 | 4096 | 2299 | 6395 | 2362 | 4096 | 2362 | 6458 | 2242 | 4096 | 2242 | 6338 | 2291 | 4096 | 2291 | 6387 | 2304 | 4096 | 2304 | 6400 | 2335 | 4096 | 2335 | 6431 | 2334 | 4096 | 2334 | 6430 | 2272 | 4101 | 2277 | 6373 | 2307 | 4096 | 2307 | 6403 | 2352 | 4097 | 2353 | 6449 | 2368 | 4096 | 2368 | 6464 | 2246 | 4096 | 2246 | 6342 | 2291 | 4096 | 2291 | 6387 | 2304 | 4096 | 2304 | 6400 | 2286 | 4096 | 2286 | 6382 | 2311 | 4096 | 2311 | 6407 | 2269 | 4096 | 2269 | 6365 | 2265 | 4096 | 2265 | 6361 | 2333 | 4096 | 2333 | 6429 | 2332 | 4096 | 2332 | 6428 | 2303 | 4097 | 2304 | 6400 | 2436 | 4098 | 2438 | 6534 | 2273 | 4096 | 2273 | 6369 | 2287 | 4096 | 2287 | 6383 | 2310 | 4096 | 2310 | 6406 | 2271 | 4096 | 2271 | 6367 | 2266 | 4096 | 2266 | 6362 | 2333 | 4096 | 2333 | 6429 | 2332 | 4096 | 2332 | 6428 | 2308 | 4096 | 2308 | 6404 | 64 | 0x7fdebc5a8ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 28552738.0 | 87675491.0 | 39015420.0 | 131072.0 | 0.0 | 238435.0 | 0 | 0 | 15129 | 1192.0 | 131081.0 | 0.0 | 10.0 | 64 | 0x7f4e1b248ec0 | 0 | 0 | 0 | 224 | 0 | 65536 | 64189 | 56 | 64 | 0x7f7afa4d8ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 10997 | 0 | 818 | 28056 | 0 | 73000.0 | 131072.0 | 0.0 | 65568.0 | 64 | 0x7f3778dc4ec0 | 1868 | 125231 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f1a1ee60ec0 | 0 | 0 | 0 | 979631 | 0 | 0 | 0 | 1041459 | 0 | 0 | 0 | 1072208 | 0 | 0 | 0 | 1214414 | 0 | 0 | 0 | 1051269 | 0 | 0 | 0 | 1051062 | 0 | 0 | 0 | 1161186 | 66 | 0 | 0 | 1207646 | 0 | 0 | 0 | 1039979 | 0 | 0 | 0 | 1013941 | 0 | 0 | 0 | 1090982 | 0 | 0 | 0 | 1166864 | 0 | 0 | 0 | 1067625 | 0 | 0 | 0 | 1044526 | 0 | 0 | 0 | 1108504 | 0 | 0 | 0 | 1055894 | 1 | 0 | 0 | 1108064 | 6 | 0 | 0 | 1210489 | 0 | 0 | 0 | 1043190 | 99 | 0 | 0 | 1213111 | 0 | 0 | 0 | 1035661 | 1 | 0 | 0 | 1173468 | 98 | 0 | 0 | 1162371 | 5 | 0 | 0 | 1172342 | 0 | 0 | 0 | 1076940 | 0 | 0 | 0 | 1088200 | 60 | 0 | 0 | 1087921 | 0 | 0 | 0 | 1094389 | 0 | 0 | 0 | 1173325 | 0 | 0 | 0 | 1080090 | 26 | 0 | 0 | 1082717 | 0 | 0 | 0 | 1099673 | 64 | 0x7fcd5a20cec0 | 32768 | 32768 | 0 | 64 | 0x7fdf9e470ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 168 | 56 | 131072.0 | 131072.0 | 0.0 | 941639.0 | 64 | 0x7fdaa7c38ec0 | 233720 | 132943 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 29214 | 29214 | 2005996.0 | 1421899.0 | 3264.0 | 172595.0 | 1130919.0 | 0.0 | 1413687.0 | 1115350.0 | 232009 | 141066 | 29214 | 0 | 29214 | 0 | 934848.0 | 504393.0 | 0.0 | 0.0 | 64 | 0x7fd12b1d8ec0 | 6363 | 0 | 4096 | 6388 | 0 | 4096 | 6368 | 0 | 4096 | 6401 | 0 | 4096 | 6380 | 0 | 4096 | 6341 | 0 | 4096 | 6380 | 0 | 4096 | 6412 | 0 | 4096 | 6414 | 0 | 4096 | 6360 | 0 | 4096 | 6392 | 0 | 4096 | 6372 | 0 | 4096 | 6399 | 0 | 4096 | 6384 | 0 | 4096 | 6344 | 0 | 4096 | 6380 | 0 | 4096 | 6403 | 0 | 4096 | 6407 | 0 | 4096 | 6404 | 0 | 4096 | 6372 | 0 | 4096 | 6424 | 0 | 4096 | 6420 | 0 | 4096 | 6391 | 0 | 4096 | 6536 | 0 | 4096 | 6372 | 0 | 4096 | 6402 | 0 | 4096 | 6410 | 0 | 4096 | 6405 | 0 | 4096 | 6370 | 0 | 4096 | 6423 | 0 | 4096 | 6421 | 0 | 4096 | 6389 | 0 | 4096 | 1412189920581155 | 1412189920601635 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f1570dbcec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131083.0 | 85469.0 | 45456.0 | 0.0 | 64 | 0x7fdc1db54ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 31463 | 27230 | 9551 | 2937 | 0 | 40426 | 201004.0 | 0.0 | 69917.0 | 131087.0 | 64 | 0x7f931b1e8ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 118801110.0 | 60068928.0 | 0.0 | 64 | 0x7f523a854ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 29385 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 201.0 | 32768.0 | 4096 | 16384 | 302 | 40302 | 1926 | 0 | 56.0 | 9.0 | 0.0 | 200114.0 | 64 | 0x7f3a11414ec0 | 0 | 3348130 | 2792 | 2792 | 0 | 3355576 | 2824 | 2824 | 0 | 4317597 | 2856 | 2856 | 0 | 4749387 | 2858 | 2858 | 0 | 2880492 | 2862 | 2862 | 0 | 3449303 | 2832 | 2832 | 0 | 3174316 | 2898 | 2898 | 0 | 3955879 | 2852 | 2852 | 0 | 3718192 | 2850 | 2850 | 0 | 2395543 | 2792 | 2792 | 0 | 3667661 | 2824 | 2824 | 0 | 5138963 | 2852 | 2852 | 0 | 2728816 | 2860 | 2860 | 0 | 3526690 | 2864 | 2864 | 0 | 3122284 | 2820 | 2820 | 0 | 4212447 | 2894 | 2894 | 0 | 4463237 | 2822 | 2822 | 0 | 4839005 | 2872 | 2872 | 0 | 2549905 | 2800 | 2800 | 0 | 3116980 | 2828 | 2828 | 0 | 5417200 | 2844 | 2844 | 0 | 3485778 | 2912 | 2912 | 0 | 2657335 | 2788 | 2788 | 0 | 3663254 | 2814 | 2814 | 0 | 3251726 | 2816 | 2816 | 0 | 4846338 | 2828 | 2828 | 0 | 3545356 | 2864 | 2864 | 0 | 2515324 | 2800 | 2800 | 0 | 3631658 | 2832 | 2832 | 0 | 3050512 | 2848 | 2848 | 0 | 3303964 | 2914 | 2914 | 0 | 3064273 | 2790 | 2790 | 64 | 0x7f89343bcec0 | 4096 | 0 | 786 | 0 | 4096 | 0 | 682 | 0 | 4096 | 0 | 1280 | 0 | 4096 | 0 | 1703 | 0 | 4096 | 0 | 629 | 0 | 4098 | 0 | 894 | 0 | 4096 | 0 | 657 | 0 | 4096 | 0 | 892 | 0 | 4096 | 0 | 297 | 0 | 4096 | 0 | 437 | 0 | 4096 | 0 | 979 | 0 | 4096 | 0 | 756 | 0 | 4096 | 0 | 567 | 0 | 4096 | 0 | 128 | 0 | 4096 | 0 | 584 | 0 | 4096 | 0 | 517 | 0 | 4098 | 0 | 230 | 0 | 4097 | 0 | 487 | 0 | 4097 | 0 | 1897 | 0 | 4096 | 0 | 2454 | 0 | 4096 | 0 | 122 | 0 | 4098 | 0 | 777 | 0 | 4096 | 0 | 30 | 0 | 4096 | 0 | 1312 | 0 | 4096 | 0 | 83 | 0 | 4096 | 0 | 462 | 0 | 4096 | 0 | 1323 | 0 | 4096 | 0 | 1509 | 0 | 4096 | 0 | 703 | 0 | 4097 | 0 | 158 | 0 | 4096 | 0 | 628 | 0 | 4096 | 0 | 34 | 0 | 64 | 0x7f083fe4cec0 | 20369713 | 18691961 | 1333688 | 344064 | 2903082 | 0 | 0 | 163840 | 832.0 | 515154.0 | 0.0 | 524288.0 | 595025.0 | 32768.0 | 1070424 | 0 | 0 | 13891 | 91078.0 | 91078.0 | 0.0 | 91078.0 | 64 | 0x7f8503d18ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65550.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f53cdd50ec0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 0 | 42482 | 0 | 0 | 64 | 0x7f3893ad8ec0 | 2192 | 4096 | 2192 | 6288 | 2177 | 4096 | 2177 | 6273 | 2152 | 4096 | 2152 | 6248 | 2181 | 4096 | 2181 | 6277 | 2172 | 4096 | 2172 | 6268 | 2160 | 4096 | 2160 | 6256 | 2161 | 4096 | 2161 | 6257 | 2162 | 4096 | 2162 | 6258 | 2166 | 4096 | 2166 | 6262 | 2193 | 4100 | 2197 | 6293 | 2180 | 4096 | 2180 | 6276 | 2217 | 4097 | 2218 | 6314 | 2183 | 4096 | 2183 | 6279 | 2176 | 4096 | 2176 | 6272 | 2160 | 4097 | 2161 | 6257 | 2159 | 4096 | 2159 | 6255 | 2160 | 4096 | 2160 | 6256 | 2150 | 4096 | 2150 | 6246 | 2160 | 4097 | 2161 | 6257 | 2177 | 4098 | 2179 | 6275 | 2147 | 4096 | 2147 | 6243 | 2209 | 4096 | 2209 | 6305 | 2182 | 4097 | 2183 | 6279 | 2188 | 4096 | 2188 | 6284 | 2190 | 4096 | 2190 | 6286 | 2163 | 4096 | 2163 | 6259 | 2146 | 4096 | 2146 | 6242 | 2159 | 4096 | 2159 | 6255 | 2175 | 4097 | 2176 | 6272 | 2150 | 4096 | 2150 | 6246 | 2212 | 4096 | 2212 | 6308 | 2179 | 4096 | 2179 | 6275 | 64 | 0x7fdebc5a8ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 57969890.0 | 201979280.0 | 47778440.0 | 131072.0 | 0.0 | 490026.0 | 0 | 0 | 23124 | 6341.0 | 131073.0 | 0.0 | 0.0 | 64 | 0x7f4e1b248ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7f7afa4d8ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 19855 | 0 | 3132 | 38216 | 0 | 69358.0 | 131072.0 | 0.0 | 45639.0 | 64 | 0x7f3778dc4ec0 | 0 | 202773 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f1a1ee60ec0 | 22 | 0 | 0 | 1535919 | 110 | 0 | 0 | 1884769 | 127 | 0 | 0 | 1735477 | 260 | 0 | 0 | 2110367 | 0 | 0 | 0 | 1751471 | 0 | 0 | 0 | 1672668 | 1293 | 0 | 0 | 2421099 | 143 | 0 | 0 | 2187979 | 0 | 0 | 0 | 1769919 | 0 | 0 | 0 | 1761306 | 248 | 0 | 0 | 1922908 | 0 | 0 | 0 | 1723399 | 15 | 0 | 0 | 1730083 | 0 | 0 | 0 | 1538376 | 1318 | 0 | 0 | 2263235 | 305 | 0 | 0 | 1964295 | 714 | 0 | 0 | 2210096 | 118 | 0 | 0 | 2298216 | 0 | 0 | 0 | 1508423 | 151 | 0 | 0 | 1776321 | 154 | 0 | 0 | 1994670 | 142 | 0 | 0 | 1865177 | 0 | 0 | 0 | 1878218 | 0 | 0 | 0 | 1723366 | 59 | 0 | 0 | 1897778 | 348 | 0 | 0 | 2164277 | 0 | 0 | 0 | 1641318 | 0 | 0 | 0 | 1689327 | 253 | 0 | 0 | 2237302 | 0 | 0 | 0 | 1429626 | 0 | 0 | 0 | 1664500 | 0 | 0 | 0 | 1779765 | 64 | 0x7fcd5a20cec0 | 32768 | 32768 | 0 | 64 | 0x7fdf9e470ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 2074337.0 | 64 | 0x7fdaa7c38ec0 | 300360 | 205594 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 37544 | 37544 | 2948437.0 | 2353334.0 | 4298.0 | 331931.0 | 1694164.0 | 0.0 | 2341567.0 | 2032467.0 | 300352 | 214577 | 37544 | 0 | 37544 | 0 | 1201408.0 | 775968.0 | 0.0 | 0.0 | 64 | 0x7fd12b1d8ec0 | 6253 | 0 | 4096 | 6260 | 0 | 4096 | 6275 | 0 | 4096 | 6268 | 0 | 4096 | 6283 | 0 | 4096 | 6263 | 0 | 4096 | 6286 | 0 | 4096 | 6282 | 0 | 4096 | 6287 | 0 | 4096 | 6249 | 0 | 4096 | 6258 | 0 | 4096 | 6282 | 0 | 4096 | 6271 | 0 | 4096 | 6283 | 0 | 4096 | 6259 | 0 | 4096 | 6290 | 0 | 4096 | 6302 | 0 | 4096 | 6263 | 0 | 4096 | 6252 | 0 | 4096 | 6270 | 0 | 4096 | 6263 | 0 | 4096 | 6283 | 0 | 4096 | 6289 | 0 | 4096 | 6262 | 0 | 4096 | 6258 | 0 | 4096 | 6304 | 0 | 4096 | 6264 | 0 | 4096 | 6257 | 0 | 4096 | 6273 | 0 | 4096 | 6267 | 0 | 4096 | 6288 | 0 | 4096 | 6295 | 0 | 4096 | 1412189920620835 | 1412189920636515 |