Files
rocm-systems/tests/workloads/ipblocks_SQ_CPC/MI100/pmc_perf.csv
T
JoseSantosAMD da506ad9b5 Pytest add mi200 to analyze workloads (#334)
* Updated links in documentation. (#328)

Updated to reflect new GitHub organization.
Fixed broken links to GitHub pages.

Signed-off-by: David Galiffi <David.Galiffi@amd.com>

* update branch for 2.x documentation builds

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* update checkout action and use concurrency instead of cancel-workflow-action

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* test addition of user option for container launch

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* remove --user option for container, try chown instead

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* fixing yaml syntax

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* reorder job step - start with checkout

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* restore missing run directive

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* Update workloads to include log.txt
Add missing MI200 workloads

Signed-off-by: Jose Santos <josantos@amd.com>

* Signed-off-by: Jose Santos <josantos@amd.com>
Add vcopy workload for tests

* Change exit codes for caught failures

Signed-off-by: Jose Santos <josantos@amd.com>

* reformat

Signed-off-by: Jose Santos <josantos@amd.com>

* Add pytest-xdist for pytest -n

Signed-off-by: Jose Santos <josantos@amd.com>

---------

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
Signed-off-by: Jose Santos <josantos@amd.com>
Co-authored-by: David Galiffi <David.Galiffi@amd.com>
Co-authored-by: Karl W. Schulz <karl.schulz@amd.com>
2024-04-01 14:30:21 -05:00

3.8 KiB

1Dispatch_IDKernel_NameGPU_IDGrid_SizeWorkgroup_SizeLDS_Per_WorkgroupScratch_Per_WorkitemArch_VGPRAccum_VGPRSGPRwave_sizeobjSQ_INSTS_SMEMSQ_INSTS_FLATSQ_INSTS_LDSSQ_INSTS_GDSSQ_INSTS_EXP_GDSSQ_INSTS_BRANCHSQ_INSTS_SENDMSGSQ_INSTSCPC_CPC_TCIU_BUSYCPC_CPC_TCIU_IDLEwave_size_1obj_1SQ_WAVES_SAVEDSQ_INSTS_SMEM_NORMSQC_TC_INST_REQSQC_TC_DATA_READ_REQSQC_TC_DATA_WRITE_REQSQC_TC_DATA_ATOMIC_REQSQC_TC_STALLSQC_TC_REQwave_size_2obj_2SQ_WAVES_LT_48SQ_WAVES_LT_32SQ_WAVES_LT_16SQ_ITEMSSQ_LDS_MEM_VIOLATIONSSQ_LDS_ATOMIC_RETURNSQ_LDS_IDX_ACTIVESQ_WAVES_RESTOREDCPC_ME1_DC0_SPI_BUSYwave_size_3obj_3SQ_ACTIVE_INST_VALUSQ_ACTIVE_INST_SCASQ_ACTIVE_INST_EXP_GDSSQ_ACTIVE_INST_MISCSQ_ACTIVE_INST_FLATSQ_INST_CYCLES_VMEM_WRSQ_INST_CYCLES_VMEM_RDSQ_INST_CYCLES_SMEMCPC_CPC_UTCL2IU_BUSYCPC_CPC_UTCL2IU_IDLEwave_size_4obj_4SQC_DCACHE_REQSQC_DCACHE_HITSSQC_DCACHE_MISSESSQC_DCACHE_MISSES_DUPLICATESQC_DCACHE_REQ_READ_1SQC_DCACHE_REQ_READ_2SQC_DCACHE_REQ_READ_4wave_size_5obj_5SQ_CYCLESSQ_BUSY_CYCLESSQ_WAVESSQ_INSTS_VMEM_WRSQ_INSTS_VMEM_RDSQ_INSTS_VMEMSQ_INSTS_SALUSQ_INSTS_VSKIPPEDGRBM_COUNTGRBM_GUI_ACTIVECPC_CPC_STAT_BUSYCPC_CPC_STAT_IDLEwave_size_6obj_6SQ_INST_CYCLES_SALUSQ_THREAD_CYCLES_VALUSQ_IFETCHSQ_LDS_BANK_CONFLICTSQ_LDS_ADDR_CONFLICTSQ_LDS_UNALIGNED_STALLSQ_WAVES_EQ_64SQ_WAVES_LT_64CPC_CPC_UTCL2IU_STALLCPC_ME1_BUSY_FOR_PACKET_DECODEwave_size_7obj_7SQC_DCACHE_REQ_READ_16SQC_ICACHE_REQSQC_ICACHE_HITSSQC_ICACHE_MISSESSQC_ICACHE_MISSES_DUPLICATESQC_DCACHE_INPUT_VALID_READYBSQC_DCACHE_ATOMICSQC_DCACHE_REQ_READ_8wave_size_8obj_8SQ_WAVE_CYCLESSQ_WAIT_ANYSQ_WAIT_INST_ANYSQ_ACTIVE_INST_ANYSQ_BUSY_CU_CYCLESSQ_INSTS_VALUSQ_ACTIVE_INST_VMEMSQ_ACTIVE_INST_LDSCPC_CPC_STAT_STALLCPC_UTCL1_STALL_ON_TRANSLATIONStart_TimestampEnd_Timestamp
20vecCopy(double*, double*, double*, int, int) [clone .kd]21048576256008816640x7f7367e2cec06553632768000163841638439321653948237640x7f17ab8acec0013107214448000192640x7fd2d09bcec00001048576000025884640x7f5bfe3d8ec01802241146880327683276816384163846553691347394640x7fab8f51cec0655366404848144032768327680640x7f5b4fdd8ec0390728241704163841638416384327684915204884048840488400640x7f8fd57d8ec0491521153433665536000163840017751640x7fbe215c0ec00655366437648147620022500640x7fba5caa0ec0250089822221927724292573604483418842163840001013558814102223757772911410222375801611
31vecCopy(double*, double*, double*, int, int) [clone .kd]21048576256008816640x7f7367e2cec06553632768000163841638439321645742609640x7f17ab8acec0013107204800048640x7fd2d09bcec00001048576000025092640x7f5bfe3d8ec018022411468803276832768163841638465536269340196640x7fab8f51cec0655366404848144032768327680640x7f5b4fdd8ec0353032239682163841638416384327684915204412844128441280640x7f8fd57d8ec0491521153433665536000163840014036640x7fbe215c0ec0065536655360019480200640x7fba5caa0ec0250393402254231621365763604483409344163840008517243614102223758820911410222375900811
42vecCopy(double*, double*, double*, int, int) [clone .kd]21048576256008816640x7f7367e2cec06553632768000163841638439321645742137640x7f17ab8acec0013107204800048640x7fd2d09bcec00001048576000025337640x7f5bfe3d8ec018022411468803276832768163841638465536271839766640x7fab8f51cec0655366404848144032768327680640x7f5b4fdd8ec0347760238950163841638416384327684915204346943469434690640x7f8fd57d8ec0491521153433665536000163840014252640x7fbe215c0ec0065536655360019380600640x7fba5caa0ec0250169392246733121891603604483405503163840008573243614102223759211311410222375939851