da506ad9b5
* Updated links in documentation. (#328) Updated to reflect new GitHub organization. Fixed broken links to GitHub pages. Signed-off-by: David Galiffi <David.Galiffi@amd.com> * update branch for 2.x documentation builds Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * update checkout action and use concurrency instead of cancel-workflow-action Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * test addition of user option for container launch Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * remove --user option for container, try chown instead Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * fixing yaml syntax Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * reorder job step - start with checkout Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * restore missing run directive Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * Update workloads to include log.txt Add missing MI200 workloads Signed-off-by: Jose Santos <josantos@amd.com> * Signed-off-by: Jose Santos <josantos@amd.com> Add vcopy workload for tests * Change exit codes for caught failures Signed-off-by: Jose Santos <josantos@amd.com> * reformat Signed-off-by: Jose Santos <josantos@amd.com> * Add pytest-xdist for pytest -n Signed-off-by: Jose Santos <josantos@amd.com> --------- Signed-off-by: David Galiffi <David.Galiffi@amd.com> Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> Signed-off-by: Jose Santos <josantos@amd.com> Co-authored-by: David Galiffi <David.Galiffi@amd.com> Co-authored-by: Karl W. Schulz <karl.schulz@amd.com>
3.8 KiB
3.8 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | SQ_INSTS_SMEM | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | SQ_INSTS | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | wave_size_1 | obj_1 | SQ_WAVES_SAVED | SQ_INSTS_SMEM_NORM | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | SQC_TC_DATA_WRITE_REQ | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | wave_size_2 | obj_2 | SQ_WAVES_LT_48 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | CPC_ME1_DC0_SPI_BUSY | wave_size_3 | obj_3 | SQ_ACTIVE_INST_VALU | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | wave_size_4 | obj_4 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | SQC_DCACHE_REQ_READ_1 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | wave_size_5 | obj_5 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_WAVES | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | SQ_INSTS_VSKIPPED | GRBM_COUNT | GRBM_GUI_ACTIVE | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | wave_size_6 | obj_6 | SQ_INST_CYCLES_SALU | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | wave_size_7 | obj_7 | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | SQC_ICACHE_MISSES_DUPLICATE | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | wave_size_8 | obj_8 | SQ_WAVE_CYCLES | SQ_WAIT_ANY | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_BUSY_CU_CYCLES | SQ_INSTS_VALU | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f7367e2cec0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 539 | 48237 | 64 | 0x7f17ab8acec0 | 0 | 131072 | 144 | 48 | 0 | 0 | 0 | 192 | 64 | 0x7fd2d09bcec0 | 0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 25884 | 64 | 0x7f5bfe3d8ec0 | 180224 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 913 | 47394 | 64 | 0x7fab8f51cec0 | 65536 | 64048 | 48 | 1440 | 32768 | 32768 | 0 | 64 | 0x7f5b4fdd8ec0 | 390728 | 241704 | 16384 | 16384 | 16384 | 32768 | 49152 | 0 | 48840 | 48840 | 48840 | 0 | 64 | 0x7f8fd57d8ec0 | 49152 | 11534336 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 17751 | 64 | 0x7fbe215c0ec0 | 0 | 65536 | 64376 | 48 | 1476 | 200225 | 0 | 0 | 64 | 0x7fba5caa0ec0 | 25008982 | 22219277 | 2429257 | 360448 | 3418842 | 163840 | 0 | 0 | 10135 | 588 | 1410222375777291 | 1410222375801611 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f7367e2cec0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 457 | 42609 | 64 | 0x7f17ab8acec0 | 0 | 131072 | 0 | 48 | 0 | 0 | 0 | 48 | 64 | 0x7fd2d09bcec0 | 0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 25092 | 64 | 0x7f5bfe3d8ec0 | 180224 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 2693 | 40196 | 64 | 0x7fab8f51cec0 | 65536 | 64048 | 48 | 1440 | 32768 | 32768 | 0 | 64 | 0x7f5b4fdd8ec0 | 353032 | 239682 | 16384 | 16384 | 16384 | 32768 | 49152 | 0 | 44128 | 44128 | 44128 | 0 | 64 | 0x7f8fd57d8ec0 | 49152 | 11534336 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 14036 | 64 | 0x7fbe215c0ec0 | 0 | 65536 | 65536 | 0 | 0 | 194802 | 0 | 0 | 64 | 0x7fba5caa0ec0 | 25039340 | 22542316 | 2136576 | 360448 | 3409344 | 163840 | 0 | 0 | 8517 | 2436 | 1410222375882091 | 1410222375900811 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f7367e2cec0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 457 | 42137 | 64 | 0x7f17ab8acec0 | 0 | 131072 | 0 | 48 | 0 | 0 | 0 | 48 | 64 | 0x7fd2d09bcec0 | 0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 25337 | 64 | 0x7f5bfe3d8ec0 | 180224 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 2718 | 39766 | 64 | 0x7fab8f51cec0 | 65536 | 64048 | 48 | 1440 | 32768 | 32768 | 0 | 64 | 0x7f5b4fdd8ec0 | 347760 | 238950 | 16384 | 16384 | 16384 | 32768 | 49152 | 0 | 43469 | 43469 | 43469 | 0 | 64 | 0x7f8fd57d8ec0 | 49152 | 11534336 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 14252 | 64 | 0x7fbe215c0ec0 | 0 | 65536 | 65536 | 0 | 0 | 193806 | 0 | 0 | 64 | 0x7fba5caa0ec0 | 25016939 | 22467331 | 2189160 | 360448 | 3405503 | 163840 | 0 | 0 | 8573 | 2436 | 1410222375921131 | 1410222375939851 |