Amber Lin
9e32cdb113
Many devices have the same counter IDs for the hardware block. Devices in the same GFX generation usually have the same block counters. No need to list each device individually. Instead, have a table to share with all devices that have the same counter IDs, and have separated tables for devices that don't have the same counter IDs. Change-Id: I857056edc6f491f61af6e9598580e5dc7d372f94
316 lines
11 KiB
C
316 lines
11 KiB
C
/*
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* Copyright © 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including
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* the next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <sys/types.h>
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#include <dirent.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "libhsakmt.h"
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#include "pmc_table.h"
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/* Unused counters - 163-167 */
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static uint32_t gfx7_sq_counter_ids[] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
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23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,
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43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62,
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63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
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83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101,
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102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
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118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,
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134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
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150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 168, 169, 170,
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171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186,
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187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202,
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203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218,
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219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234,
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235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250
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};
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/* Unused counters - 166, 292 - 297 */
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static uint32_t gfx8_sq_counter_ids[] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
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23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42,
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43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62,
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63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
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83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101,
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102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
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118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,
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134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
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150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165,
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167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182,
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183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
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199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
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215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230,
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231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246,
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247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262,
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263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278,
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279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 298
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};
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/* Polaris 10/11 have the same SQ cpunter IDs but different from other gfx8's. */
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/* Unused counters - 167 and 275 are *_DUMMY_LAST */
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static uint32_t gfx8_pl_sq_counter_ids[] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
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22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40,
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41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
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60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
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79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
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98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
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113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
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128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
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143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157,
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158, 159, 160, 161, 162, 163, 164, 165, 168, 169, 170, 171, 172, 173, 174,
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175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189,
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190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204,
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205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219,
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220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234,
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235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249,
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250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264,
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265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 276, 277, 278, 279, 280,
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281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295
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};
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static struct perf_counter_block kaveri_blocks[PERFCOUNTER_BLOCKID__MAX] = {
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[PERFCOUNTER_BLOCKID__SQ] = {
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.num_of_slots = 8,
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.num_of_counters = sizeof(gfx7_sq_counter_ids) /
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sizeof(*gfx7_sq_counter_ids),
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.counter_ids = gfx7_sq_counter_ids,
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.counter_size_in_bits = 64,
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.counter_mask = BITMASK(64)
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},
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};
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static struct perf_counter_block carrizo_blocks[PERFCOUNTER_BLOCKID__MAX] = {
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[PERFCOUNTER_BLOCKID__SQ] = {
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.num_of_slots = 8,
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.num_of_counters = sizeof(gfx8_sq_counter_ids) /
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sizeof(*gfx8_sq_counter_ids),
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.counter_ids = gfx8_sq_counter_ids,
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.counter_size_in_bits = 64,
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.counter_mask = BITMASK(64)
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},
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};
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static struct perf_counter_block fiji_blocks[PERFCOUNTER_BLOCKID__MAX] = {
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[PERFCOUNTER_BLOCKID__SQ] = {
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.num_of_slots = 8,
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.num_of_counters = sizeof(gfx8_sq_counter_ids) /
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sizeof(*gfx8_sq_counter_ids),
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.counter_ids = gfx8_sq_counter_ids,
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.counter_size_in_bits = 64,
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.counter_mask = BITMASK(64)
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},
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};
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static struct perf_counter_block hawaii_blocks[PERFCOUNTER_BLOCKID__MAX] = {
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[PERFCOUNTER_BLOCKID__SQ] = {
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.num_of_slots = 8,
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.num_of_counters = sizeof(gfx7_sq_counter_ids) /
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sizeof(*gfx7_sq_counter_ids),
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.counter_ids = gfx7_sq_counter_ids,
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.counter_size_in_bits = 64,
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.counter_mask = BITMASK(64)
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},
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};
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static struct perf_counter_block polaris_blocks[PERFCOUNTER_BLOCKID__MAX] = {
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[PERFCOUNTER_BLOCKID__SQ] = {
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.num_of_slots = 8,
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.num_of_counters = sizeof(gfx8_pl_sq_counter_ids) /
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sizeof(*gfx8_pl_sq_counter_ids),
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.counter_ids = gfx8_pl_sq_counter_ids,
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.counter_size_in_bits = 64,
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.counter_mask = BITMASK(64)
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},
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};
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/* Current APUs only have one IOMMU. If NUMA is introduced to APUs, we'll need
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* to expand the struct here to an array.
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*/
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static struct perf_counter_block iommu_block;
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uint32_t pmc_table_get_max_concurrent(int block_id)
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{
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switch (block_id) {
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case PERFCOUNTER_BLOCKID__IOMMUV2:
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return iommu_block.num_of_slots;
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default:
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return 0;
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}
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}
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static HSAKMT_STATUS
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alloc_pmc_blocks_iommu(void)
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{
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DIR *dir;
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struct dirent *dent;
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const char sysfs_amdiommu_event_path[] =
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"/sys/bus/event_source/devices/amd_iommu/events";
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/* Counter source in IOMMU's Counter Bank Addressing register is 8 bits,
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* so the biggest counter number/id possible is 0xff.
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*/
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const int max_counter_id = 0xff;
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char path[256];
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const int len = sizeof(path);
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FILE *file;
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int num;
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char counter_id[max_counter_id + 1];
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HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS;
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uint32_t *ptr;
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struct perf_counter_block *block = &iommu_block;
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memset(block, 0, sizeof(struct perf_counter_block));
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dir = opendir(sysfs_amdiommu_event_path);
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if (!dir)
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goto out;
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memset(counter_id, 0, max_counter_id + 1);
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while ((dent = readdir(dir))) {
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if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, ".."))
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continue;
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if (snprintf(path, len, "%s/%s", sysfs_amdiommu_event_path,
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dent->d_name) >= len) {
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fprintf(stderr, "Increase path length.\n");
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ret = HSAKMT_STATUS_NO_MEMORY;
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goto out;
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}
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file = fopen(path, "r");
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if (!file) {
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ret = HSAKMT_STATUS_ERROR;
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goto out;
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}
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if (fscanf(file, "csource=0x%x", &num) != 1) {
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ret = HSAKMT_STATUS_ERROR;
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fclose(file);
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goto out;
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}
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if (num > max_counter_id)
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/* This should never happen. If it does, check IOMMU driver. */
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fprintf(stderr,
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"Error: max_counter_id %d is set too small.\n",
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max_counter_id);
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else {
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counter_id[num] = 1;
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++block->num_of_counters;
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}
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fclose(file);
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}
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block->counter_ids = malloc(sizeof(uint32_t) * block->num_of_counters);
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if (!block->counter_ids) {
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ret = HSAKMT_STATUS_NO_MEMORY;
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goto out;
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}
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ptr = block->counter_ids;
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for (num = 0; num < (max_counter_id + 1); num++) {
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if (counter_id[num]) {
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ptr[0] = num;
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++ptr;
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}
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}
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if (snprintf(path, len, "%s/%d/%s",
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"/sys/devices/virtual/kfd/kfd/topology/nodes",
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0, /* IOMMU is in node 0. Change this if NUMA is introduced to APU. */
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"perf/iommu/max_concurrent") >= len) {
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fprintf(stderr, "Increase path length\n");
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ret = HSAKMT_STATUS_NO_MEMORY;
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goto out;
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};
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file = fopen(path, "r");
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if (!file) {
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ret = HSAKMT_STATUS_ERROR;
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goto out;
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}
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if (fscanf(file, "%d", &block->num_of_slots) != 1)
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ret = HSAKMT_STATUS_ERROR;
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fclose(file);
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out:
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if (dir)
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closedir(dir);
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return ret;
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}
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HSAKMT_STATUS alloc_pmc_blocks(void)
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{
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return alloc_pmc_blocks_iommu();
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}
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void free_pmc_blocks(void)
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{
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if (iommu_block.counter_ids)
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free(iommu_block.counter_ids);
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iommu_block.counter_ids = NULL;
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iommu_block.num_of_counters = 0;
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}
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HSAKMT_STATUS
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get_block_properties(uint32_t node_id,
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enum perf_block_id block_id,
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struct perf_counter_block *block)
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{
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uint16_t dev_id = get_device_id_by_node(node_id);
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enum asic_family_type asic;
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if (block_id > PERFCOUNTER_BLOCKID__MAX ||
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block_id < PERFCOUNTER_BLOCKID__FIRST)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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if (block_id == PERFCOUNTER_BLOCKID__IOMMUV2) {
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*block = iommu_block;
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return HSAKMT_STATUS_SUCCESS;
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}
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if (topology_get_asic_family(dev_id, &asic) != HSAKMT_STATUS_SUCCESS)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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switch (asic) {
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case CHIP_KAVERI:
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*block = kaveri_blocks[block_id];
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break;
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case CHIP_HAWAII:
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*block = hawaii_blocks[block_id];
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break;
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case CHIP_CARRIZO:
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*block = carrizo_blocks[block_id];
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break;
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case CHIP_FIJI:
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*block = fiji_blocks[block_id];
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break;
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case CHIP_POLARIS10:
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case CHIP_POLARIS11:
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*block = polaris_blocks[block_id];
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break;
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default:
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return HSAKMT_STATUS_INVALID_PARAMETER;
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}
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return HSAKMT_STATUS_SUCCESS;
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}
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