Pengda Xie
371 خطوط
23 KiB
C++
371 خطوط
23 KiB
C++
/* Copyright (c) 2009 - 2025 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#ifndef FLAGS_HPP_
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#define FLAGS_HPP_
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// clang-format off
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#define RUNTIME_FLAGS(debug,release,release_on_stg) \
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\
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release(int, AMD_LOG_LEVEL, 0, \
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"The default log level") \
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release(uint, AMD_LOG_MASK, 0X7FFFFFFF, \
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"The mask to enable specific kinds of logs") \
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release(cstring, AMD_LOG_LEVEL_FILE, "", \
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"Set output file for AMD_LOG_LEVEL, Default is stderr") \
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release(size_t, AMD_LOG_LEVEL_SIZE, 2048, \
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"The max size of AMD_LOG generated in MB if printed to a file") \
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debug(uint, DEBUG_GPU_FLAGS, 0, \
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"The debug options for GPU device") \
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release(size_t, CQ_THREAD_STACK_SIZE, 256*Ki, /* @todo: that much! */ \
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"The default command queue thread stack size") \
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release(int, GPU_MAX_WORKGROUP_SIZE, 0, \
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"Maximum number of workitems in a workgroup for GPU, 0 -use default") \
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debug(bool, CPU_MEMORY_GUARD_PAGES, false, \
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"Use guard pages for CPU memory") \
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debug(size_t, CPU_MEMORY_GUARD_PAGE_SIZE, 64, \
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"Size in KB of CPU memory guard page") \
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debug(size_t, CPU_MEMORY_ALIGNMENT_SIZE, 256, \
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"Size in bytes for the default alignment for guarded memory on CPU") \
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debug(size_t, PARAMETERS_MIN_ALIGNMENT, NATIVE_ALIGNMENT_SIZE, \
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"Minimum alignment required for the abstract parameters stack") \
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debug(size_t, MEMOBJ_BASE_ADDR_ALIGN, 4*Ki, \
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"Alignment of the base address of any allocate memory object") \
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release(uint, ROC_HMM_FLAGS, 0, \
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"ROCm HMM configuration flags") \
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release(cstring, GPU_DEVICE_ORDINAL, "", \
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"Select the device ordinal (comma seperated list of available devices)") \
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release(bool, REMOTE_ALLOC, false, \
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"Use remote memory for the global heap allocation") \
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release(uint, GPU_CP_DMA_COPY_SIZE, 1, \
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"Set maximum size of CP DMA copy in KiB") \
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release(uint, GPU_MAX_HEAP_SIZE, 100, \
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"Set maximum size of the GPU heap to % of board memory") \
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release(uint, GPU_STAGING_BUFFER_SIZE, 4, \
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"Size of the GPU staging buffer in MiB") \
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release(bool, GPU_DUMP_BLIT_KERNELS, false, \
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"Dump the kernels for blit manager") \
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release(uint, GPU_BLIT_ENGINE_TYPE, 0x0, \
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"Blit engine type: 0 - Default, 1 - Host, 2 - CAL, 3 - Kernel") \
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release(bool, GPU_FLUSH_ON_EXECUTION, false, \
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"Submit commands to HW on every operation. 0 - Disable, 1 - Enable") \
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release(bool, CL_KHR_FP64, true, \
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"Enable/Disable support for double precision") \
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release(cstring, AMD_OCL_BUILD_OPTIONS, 0, \
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"Set clBuildProgram() and clCompileProgram()'s options (override)") \
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release(cstring, AMD_OCL_BUILD_OPTIONS_APPEND, 0, \
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"Append clBuildProgram() and clCompileProgram()'s options") \
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release(cstring, AMD_OCL_LINK_OPTIONS, 0, \
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"Set clLinkProgram()'s options (override)") \
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release(cstring, AMD_OCL_LINK_OPTIONS_APPEND, 0, \
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"Append clLinkProgram()'s options") \
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debug(cstring, AMD_OCL_SUBST_OBJFILE, 0, \
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"Specify binary substitution config file for OpenCL") \
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release(size_t, GPU_PINNED_XFER_SIZE, 32, \
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"The pinned buffer size for pinning in read/write transfers in MiB") \
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release(size_t, GPU_PINNED_MIN_XFER_SIZE, 128, \
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"The minimal buffer size for pinned read/write transfers in MiB") \
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release(size_t, GPU_RESOURCE_CACHE_SIZE, 64, \
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"The resource cache size in MB") \
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release(size_t, GPU_MAX_SUBALLOC_SIZE, 4096, \
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"The maximum size accepted for suballocations in KB") \
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release(size_t, GPU_NUM_MEM_DEPENDENCY, 256, \
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"Number of memory objects for dependency tracking") \
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release(size_t, GPU_XFER_BUFFER_SIZE, 0, \
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"Transfer buffer size for image copy optimization in KB") \
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release(bool, GPU_IMAGE_DMA, true, \
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"Enable DRM DMA for image transfers") \
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release(uint, GPU_SINGLE_ALLOC_PERCENT, 100, \
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"Maximum size of a single allocation as percentage of total") \
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release(uint, GPU_NUM_COMPUTE_RINGS, 2, \
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"GPU number of compute rings. 0 - disabled, 1 , 2,.. - the number of compute rings") \
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release(bool, AMD_OCL_WAIT_COMMAND, false, \
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"1 = Enable a wait for every submitted command") \
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release(uint, GPU_PRINT_CHILD_KERNEL, 0, \
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"Prints the specified number of the child kernels") \
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release(bool, GPU_USE_DEVICE_QUEUE, false, \
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"Use a dedicated device queue for the actual submissions") \
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release(bool, AMD_THREAD_TRACE_ENABLE, true, \
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"Enable thread trace extension") \
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release(uint, OPENCL_VERSION, 200, \
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"Force GPU opencl version") \
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release(bool, HSA_LOCAL_MEMORY_ENABLE, true, \
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"Enable HSA device local memory usage") \
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release(uint, HSA_KERNARG_POOL_SIZE, 1024 * 1024, \
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"Kernarg pool size") \
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release(bool, GPU_MIPMAP, true, \
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"Enables GPU mipmap extension") \
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release(uint, GPU_ENABLE_PAL, 2, \
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"Enables PAL backend. 0 - ROC, 1 - PAL, 2 - ROC or PAL") \
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release(bool, DISABLE_DEFERRED_ALLOC, false, \
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"Disables deferred memory allocation on device") \
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release(int, AMD_GPU_FORCE_SINGLE_FP_DENORM, -1, \
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"Force denorm for single precision: -1 - don't force, 0 - disable, 1 - enable") \
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release(uint, OCL_SET_SVM_SIZE, 4*16384, \
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"set SVM space size for discrete GPU") \
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release(uint, GPU_WAVES_PER_SIMD, 0, \
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"Force the number of waves per SIMD (1-10)") \
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release(bool, OCL_STUB_PROGRAMS, false, \
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"1 = Enables OCL programs stubing") \
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release(bool, GPU_ANALYZE_HANG, false, \
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"1 = Enables GPU hang analysis") \
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release(uint, GPU_MAX_REMOTE_MEM_SIZE, 2, \
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"Maximum size (in Ki) that allows device memory substitution with system") \
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release(bool, GPU_ADD_HBCC_SIZE, false, \
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"Add HBCC size to the reported device memory") \
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release(bool, PAL_DISABLE_SDMA, false, \
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"1 = Disable SDMA for PAL") \
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release(uint, PAL_RGP_DISP_COUNT, 10000, \
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"The number of dispatches for RGP capture with SQTT") \
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release(uint, PAL_MALL_POLICY, 0, \
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"Controls the behaviour of allocations with respect to the MALL" \
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"0 = MALL policy is decided by KMD" \
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"1 = Allocations are never put through the MALL" \
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"2 = Allocations will always be put through the MALL") \
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release(bool, GPU_ENABLE_WAVE32_MODE, true, \
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"Enables Wave32 compilation in HW if available") \
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release(bool, GPU_ENABLE_HW_P2P, false, \
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"Enables HW P2P path") \
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release(bool, GPU_ENABLE_COOP_GROUPS, true, \
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"Enables cooperative group launch") \
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release(uint, GPU_MAX_COMMAND_BUFFERS, 8, \
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"The maximum number of command buffers allocated per queue") \
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release(uint, GPU_MAX_HW_QUEUES, 4, \
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"The maximum number of HW queues allocated per device") \
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release(bool, GPU_IMAGE_BUFFER_WAR, true, \
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"Enables image buffer workaround") \
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release(cstring, HIP_VISIBLE_DEVICES, "", \
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"Only devices whose index is present in the sequence are visible to HIP") \
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release(cstring, CUDA_VISIBLE_DEVICES, "", \
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"Only devices whose index is present in the sequence are visible to CUDA") \
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release(bool, GPU_ENABLE_WGP_MODE, true, \
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"Enables WGP Mode in HW if available") \
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release(bool, GPU_DUMP_CODE_OBJECT, false, \
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"Enable dump code object") \
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release(uint, GPU_MAX_USWC_ALLOC_SIZE, 2048, \
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"Set a limit in Mb on the maximum USWC allocation size" \
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"-1 = No limit") \
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release(uint, AMD_SERIALIZE_KERNEL, 0, \
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"Serialize kernel enqueue, 0x1 = Wait for completion before enqueue" \
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"0x2 = Wait for completion after enqueue 0x3 = both") \
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release(uint, AMD_SERIALIZE_COPY, 0, \
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"Serialize copies, 0x1 = Wait for completion before enqueue" \
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"0x2 = Wait for completion after enqueue 0x3 = both") \
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release(uint, HIP_LAUNCH_BLOCKING, 0, \
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"Serialize kernel enqueue 0x1 = Wait for completion after enqueue," \
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"same as AMD_SERIALIZE_KERNEL=2") \
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release(bool, PAL_ALWAYS_RESIDENT, false, \
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"Force memory resources to become resident at allocation time") \
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release(uint, HIP_HOST_COHERENT, 0, \
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"Coherent memory in hipHostMalloc, 0x1 = memory is coherent with host"\
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"0x0 = memory is not coherent between host and GPU") \
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release(uint, AMD_OPT_FLUSH, 1, \
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"Kernel flush option , 0x0 = Use system-scope fence operations." \
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"0x1 = Use device-scope fence operations when possible.") \
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release(bool, AMD_DIRECT_DISPATCH, false, \
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"Enable direct kernel dispatch.") \
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release(uint, HIP_HIDDEN_FREE_MEM, 0, \
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"Reserve free mem reporting in Mb" \
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"0 = Disable") \
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release(size_t, GPU_FORCE_BLIT_COPY_SIZE, 16, \
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"Use Blit until this size(in KB) for copies") \
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release(uint, ROC_ACTIVE_WAIT_TIMEOUT, 0, \
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"Forces active wait of GPU interrup for the timeout(us)") \
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release(bool, ROC_ENABLE_LARGE_BAR, true, \
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"Enable Large Bar if supported by the device") \
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release(bool, ROC_CPU_WAIT_FOR_SIGNAL, true, \
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"Enable CPU wait for dependent HSA signals.") \
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release(bool, ROC_SYSTEM_SCOPE_SIGNAL, true, \
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"Enable system scope for signals (uses interrupts).") \
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release(bool, GPU_FORCE_QUEUE_PROFILING, false, \
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"Force command queue profiling by default") \
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release(bool, HIP_MEM_POOL_SUPPORT, true, \
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"Enables memory pool support in HIP") \
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release(bool, HIP_MEM_POOL_USE_VM, true, \
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"Enables memory pool support in HIP") \
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release(bool, DEBUG_HIP_MEM_POOL_VMHEAP, true, \
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"Enables virtual memory for memory pools") \
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release(bool, PAL_HIP_IPC_FLAG, true, \
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"Enable interprocess flag for device allocation in PAL HIP") \
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release(uint, PAL_FORCE_ASIC_REVISION, 0, \
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"Force a specific asic revision for all devices") \
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release(bool, PAL_EMBED_KERNEL_MD, false, \
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"Enables writing kernel metadata into command buffers.") \
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release(cstring, ROC_GLOBAL_CU_MASK, "", \
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"Sets a global CU mask (entered as hex value) for all queues," \
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"Each active bit represents using one CU (e.g., 0xf enables only 4 CUs)") \
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release(size_t, PAL_PREPINNED_MEMORY_SIZE, 64, \
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"Size in KBytes of prepinned memory") \
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release(bool, AMD_CPU_AFFINITY, false, \
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"Reset CPU affinity of any runtime threads") \
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release(bool, ROC_USE_FGS_KERNARG, true, \
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"Use fine grain kernel args segment for supported asics") \
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release(uint, ROC_P2P_SDMA_SIZE, 1024, \
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"The minimum size in KB for P2P transfer with SDMA") \
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release(uint, ROC_AQL_QUEUE_SIZE, 16384, \
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"AQL queue size in AQL packets") \
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release(uint, ROC_SIGNAL_POOL_SIZE, 64, \
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"Initial size of HSA signal pool") \
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release(uint, DEBUG_CLR_LIMIT_BLIT_WG, 16, \
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"Limit the number of workgroups in blit operations") \
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release(bool, DEBUG_CLR_BLIT_KERNARG_OPT, false, \
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"Enable blit kernel arguments optimization") \
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release(bool, ROC_SKIP_KERNEL_ARG_COPY, false, \
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"If true, then runtime can skip kernel arg copy") \
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release(bool, GPU_STREAMOPS_CP_WAIT, false, \
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"Force the stream wait memory operation to wait on CP.") \
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release(bool, HIPRTC_USE_RUNTIME_UNBUNDLER, false, \
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"Set this to true to force runtime unbundler in hiprtc.") \
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release(size_t, HIP_INITIAL_DM_SIZE, 8 * Mi, \
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"Set initial heap size for device malloc.") \
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release(bool, HIP_FORCE_DEV_KERNARG, true, \
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"Force device mem for kernel args.") \
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release(bool, DEBUG_CLR_GRAPH_PACKET_CAPTURE, true, \
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"Enable/Disable graph packet capturing") \
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release(bool, GPU_DEBUG_ENABLE, false, \
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"Enables collection of extra info for debugger at some perf cost") \
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release(cstring, HIPRTC_COMPILE_OPTIONS_APPEND, "", \
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"Set compile options needed for hiprtc compilation") \
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release(cstring, HIPRTC_LINK_OPTIONS_APPEND, "", \
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"Set link options needed for hiprtc compilation") \
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release(bool, HIP_VMEM_MANAGE_SUPPORT, true, \
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"Virtual Memory Management Support") \
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release(bool, DEBUG_HIP_GRAPH_DOT_PRINT, false, \
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"Enable/Disable graph debug dot print dump") \
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release(bool, DEBUG_HIP_FORCE_ASYNC_QUEUE, false, \
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"Forces grpahs into async queue mode. DEBUG_HIP_FORCE_GRAPH_QUEUES must be 1") \
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release(uint, DEBUG_HIP_FORCE_GRAPH_QUEUES, 4, \
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"Forces the number of streams for the graph parallel execution") \
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release(uint, DEBUG_HIP_GRAPH_BATCH_SIZE, 256, \
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"Number of graph nodes to batch at a time") \
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release(uint, DEBUG_HIP_BLOCK_SYNC, 50, \
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"Blocks synchronization on CPU until the callback processing is done")\
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release(uint, DEBUG_CLR_MAX_BATCH_SIZE, 1000, \
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"Forces the callback to clean-up CPU submission queue") \
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release(bool, DEBUG_CLR_SYSMEM_POOL, false, \
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"Use sysmem pool implementation in runtime for amd commands") \
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release(bool, DEBUG_HIP_KERNARG_COPY_OPT, true, \
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"Enable/Disable multiple kern arg copies") \
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release(bool, DEBUG_CLR_KERNARG_HDP_FLUSH_WA, false, \
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"Toggle kernel arg copy workaround") \
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release(bool, DEBUG_HIP_DYNAMIC_QUEUES, false, \
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"Forces dynamic queue management") \
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release(uint, HIP_SKIP_ABORT_ON_GPU_ERROR, true, \
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"Set this to true, to avoid host side abort for GPU errors") \
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release(bool, HIP_FORCE_SPIRV_CODEOBJECT, false, \
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"Force use of SPIRV instead of device specific code object.") \
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release(uint, DEBUG_CLR_BATCH_CPU_SYNC_SIZE, 8, \
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"Forces the minimum batch size for CPU sync") // clang-format on
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namespace amd {
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extern bool IS_HIP;
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extern bool IS_LEGACY;
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//! \addtogroup Utils
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// @{
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struct Flag {
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enum Type {
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Tinvalid = 0,
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Tbool, //!< A boolean type flag (true, false).
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Tint, //!< An integer type flag (signed).
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Tuint, //!< An integer type flag (unsigned).
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Tsize_t, //!< A size_t type flag.
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Tcstring //!< A string type flag.
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};
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#define DEFINE_FLAG_NAME(type, name, value, help) k##name,
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enum Name { RUNTIME_FLAGS(DEFINE_FLAG_NAME, DEFINE_FLAG_NAME, DEFINE_FLAG_NAME) numFlags_ };
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#undef DEFINE_FLAG_NAME
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#define CAN_SET(type, name, v, h) static const bool cannotSet##name = false;
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#define CANNOT_SET(type, name, v, h) static const bool cannotSet##name = true;
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#ifdef DEBUG
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RUNTIME_FLAGS(CAN_SET, CAN_SET, CAN_SET)
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#else // !DEBUG
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RUNTIME_FLAGS(CANNOT_SET, CAN_SET, CANNOT_SET)
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#endif // !DEBUG
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#undef CAN_SET
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#undef CANNOT_SET
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private:
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static Flag flags_[];
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public:
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static char* envstr_;
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const char* name_;
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const void* value_;
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Type type_;
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bool isDefault_;
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public:
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static bool init();
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static void tearDown();
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bool setValue(const char* value);
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static bool isDefault(Name name) { return flags_[name].isDefault_; }
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};
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#define flagIsDefault(name) (amd::Flag::cannotSet##name || amd::Flag::isDefault(amd::Flag::k##name))
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#define setIfNotDefault(var, opt, other) \
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if (!flagIsDefault(opt)) \
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var = (opt); \
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else \
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var = (other);
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// @}
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} // namespace amd
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#ifdef _WIN32
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#define EXPORT_FLAG extern "C" __declspec(dllexport)
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#else // !_WIN32
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#ifdef BUILD_STATIC_LIBS
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#define EXPORT_FLAG extern
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#else
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#define EXPORT_FLAG extern "C"
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#endif
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namespace amd::flags {
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#endif // !_WIN32
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#define DECLARE_RELEASE_FLAG(type, name, value, help) EXPORT_FLAG type name;
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#ifdef DEBUG
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#define DECLARE_DEBUG_FLAG(type, name, value, help) EXPORT_FLAG type name;
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#else // !DEBUG
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#define DECLARE_DEBUG_FLAG(type, name, value, help) const type name = value;
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#endif // !DEBUG
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RUNTIME_FLAGS(DECLARE_DEBUG_FLAG, DECLARE_RELEASE_FLAG, DECLARE_DEBUG_FLAG);
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#undef DECLARE_DEBUG_FLAG
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#undef DECLARE_RELEASE_FLAG
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#ifndef _WIN32
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}
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using namespace amd::flags;
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#endif // !_WIN32
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#endif /*FLAGS_HPP_*/
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