Kent Russell
d64e33520f
Fix some potentially unreleased memory, null value checks, files not closed, and other such issues reported by codeql Change-Id: Ia679aff97a773a642d8c8cbadeae30955554a62e Signed-off-by: Kent Russell <kent.russell@amd.com>
361 строка
11 KiB
C++
Исполняемый файл
361 строка
11 KiB
C++
Исполняемый файл
/*
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* =============================================================================
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* ROC Runtime Conformance Release License
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* =============================================================================
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* The University of Illinois/NCSA
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* Open Source License (NCSA)
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*
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* Copyright (c) 2017, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Developed by:
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*
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* AMD Research and AMD ROC Software Development
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*
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* Advanced Micro Devices, Inc.
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*
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* www.amd.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal with the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimers.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimers in
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* the documentation and/or other materials provided with the distribution.
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* - Neither the names of <Name of Development Group, Name of Institution>,
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* nor the names of its contributors may be used to endorse or promote
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* products derived from this Software without specific prior written
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* permission.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS WITH THE SOFTWARE.
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*
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*/
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#include <fcntl.h>
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#include <algorithm>
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#include <string>
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#include "suites/performance/enqueueLatency.h"
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#include "common/base_rocr_utils.h"
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#include "common/common.h"
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#include "common/os.h"
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#include "common/helper_funcs.h"
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#include "common/hsatimer.h"
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#include "gtest/gtest.h"
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#include "hsa/hsa.h"
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#define RET_IF_HSA_ERR(err) { \
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if ((err) != HSA_STATUS_SUCCESS) { \
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const char* msg = 0; \
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hsa_status_string(err, &msg); \
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std::cout << "hsa api call failure at line " << __LINE__ << ", file: " << \
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__FILE__ << ". Call returned " << err << std::endl; \
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std::cout << msg << std::endl; \
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return (err); \
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} \
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}
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EnqueueLatency::
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EnqueueLatency(bool enqueueSinglePacket) : TestBase(),
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enqueue_single_(enqueueSinglePacket) {
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queue_size_ = 0;
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#if ROCRTST_EMULATOR_BUILD
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num_of_pkts_ = 2;
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set_num_iteration(1);
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#else
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num_of_pkts_ = 100000;
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set_num_iteration(100);
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#endif
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memset(&aql(), 0, sizeof(hsa_kernel_dispatch_packet_t));
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enqueue_time_mean_ = 0.0;
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std::string name;
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std::string desc;
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name = "Average Enqueue Time";
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desc = "This test measures the time when the packet enqueue to the"
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" queue and before the door bell is ring to notify the command processor "
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"to execute the packet";
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if (enqueueSinglePacket) {
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name += ", Single Packet";
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desc += " One Packet at a time in queue.";
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} else {
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name += ", Multiple Packets";
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desc += " Multiple i.e. maximum Packets equeued to queue at one time";
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}
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set_title(name);
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set_description(desc);
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}
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EnqueueLatency::~EnqueueLatency() {
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}
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void EnqueueLatency::SetUp() {
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hsa_status_t err;
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TestBase::SetUp();
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// If it indicates to use default signal, set env var properly
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err = SetDefaultAgents(this);
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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}
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void EnqueueLatency::Run() {
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if (!rocrtst::CheckProfile(this)) {
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return;
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}
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hsa_status_t err;
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TestBase::Run();
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// find all gpu agents
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std::vector<hsa_agent_t> gpus;
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err = hsa_iterate_agents(rocrtst::IterateGPUAgents, &gpus);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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for (unsigned int i = 0 ; i< gpus.size(); ++i) {
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hsa_agent_t* gpu_dev = &gpus[i];
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char agent_name[64];
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err = hsa_agent_get_info(*gpu_dev, HSA_AGENT_INFO_NAME, agent_name);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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set_agent_name(agent_name);
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// Create a queue
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hsa_queue_t* q = nullptr;
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rocrtst::CreateQueue(*gpu_dev, &q);
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ASSERT_NE(q, nullptr);
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set_main_queue(q);
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set_kernel_file_name("dispatch_time_kernels.hsaco");
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set_kernel_name("empty_kernel");
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err = rocrtst::LoadKernelFromObjFile(this, gpu_dev);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Fill up the kernel packet except header
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err = rocrtst::InitializeAQLPacket(this, &aql());
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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aql().workgroup_size_x = 1;
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aql().grid_size_x = 1;
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// Here, modify the batch size if it is larger than the queue size
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if (enqueue_single_) {
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EnqueueSinglePacket();
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} else {
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hsa_status_t err;
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uint32_t size = 0;
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err = hsa_agent_get_info(*gpu_dev, HSA_AGENT_INFO_QUEUE_MAX_SIZE, &size);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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num_of_pkts_ = num_of_pkts_ > size ? size : num_of_pkts_;
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EnqueueMultiPackets();
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}
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hsa_queue_destroy(q);
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set_main_queue(nullptr);
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}
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}
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size_t EnqueueLatency::RealIterationNum() {
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return num_iteration() * 1.2 + 1;
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}
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void EnqueueLatency::EnqueueSinglePacket() {
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std::vector<double> timer;
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int it = RealIterationNum();
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const uint32_t queue_mask = main_queue()->size - 1;
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// queue should be empty
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ASSERT_EQ(hsa_queue_load_read_index_scacquire(main_queue()),
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hsa_queue_load_write_index_scacquire(main_queue()));
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hsa_kernel_dispatch_packet_t *q_base_addr =
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reinterpret_cast<hsa_kernel_dispatch_packet_t *>(
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main_queue()->base_address);
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rocrtst::PerfTimer p_timer;
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for (int i = 0; i < it; i++) {
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// Get timing stamp and ring the doorbell to dispatch the kernel.
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int id = p_timer.CreateTimer();
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p_timer.StartTimer(id);
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// Obtain the current queue write index.
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uint64_t index = hsa_queue_add_write_index_relaxed(main_queue(), 1);
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ASSERT_LT(index, main_queue()->size + index);
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// Write the aql packet at the calculated queue index address.
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rocrtst::WriteAQLToQueueLoc(main_queue(), index, &aql());
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rocrtst::AtomicSetPacketHeader(
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HSA_PACKET_TYPE_KERNEL_DISPATCH << HSA_PACKET_HEADER_TYPE,
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aql().setup,
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reinterpret_cast<hsa_kernel_dispatch_packet_t *>
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(&(q_base_addr)[index & queue_mask]));
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p_timer.StopTimer(id);
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timer.push_back(p_timer.ReadTimer(id));
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hsa_signal_store_screlease(main_queue()->doorbell_signal, index);
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// Wait on the dispatch signal until the kernel is finished.
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while (hsa_signal_wait_scacquire(aql().completion_signal,
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HSA_SIGNAL_CONDITION_LT, 1, (uint64_t) - 1, HSA_WAIT_STATE_ACTIVE)) {
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}
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hsa_signal_store_screlease(aql().completion_signal, 1);
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if (verbosity() >= VERBOSE_PROGRESS) {
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std::cout << ".";
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fflush(stdout);
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}
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}
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if (verbosity() >= VERBOSE_PROGRESS) {
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std::cout << std::endl;
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}
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// Abandon the first result and after sort, delete the last 2% value
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timer.erase(timer.begin());
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std::sort(timer.begin(), timer.end());
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timer.erase(timer.begin() + num_iteration(), timer.end());
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enqueue_time_mean_ = rocrtst::CalcMean(timer);
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return;
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}
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void EnqueueLatency::EnqueueMultiPackets() {
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std::vector<double> timer;
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int it = RealIterationNum();
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const uint32_t queue_mask = main_queue()->size - 1;
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// queue should be empty
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ASSERT_EQ(hsa_queue_load_read_index_scacquire(main_queue()),
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hsa_queue_load_write_index_scacquire(main_queue()));
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rocrtst::PerfTimer p_timer;
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hsa_kernel_dispatch_packet_t *q_base_addr =
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reinterpret_cast<hsa_kernel_dispatch_packet_t *>(
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main_queue()->base_address);
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for (int i = 0; i < it; i++) {
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// Get timing stamp and ring the doorbell to dispatch the kernel.
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int id = p_timer.CreateTimer();
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p_timer.StartTimer(id);
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uint64_t* index =
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reinterpret_cast<uint64_t*>(malloc(sizeof(uint64_t) * num_of_pkts_));
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ASSERT_NE(index, nullptr);
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hsa_signal_store_screlease(aql().completion_signal, num_of_pkts_);
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for (uint32_t j = 0; j < num_of_pkts_; j++) {
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// index[j] = hsa_queue_add_write_index_scacq_screl(main_queue(), 1);
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index[j] = hsa_queue_add_write_index_relaxed(main_queue(), 1);
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// Write the aql packet at the calculated queue index address.
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rocrtst::WriteAQLToQueueLoc(main_queue(), index[j], &aql());
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}
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// Write the aql packet at the calculated queue index address.
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rocrtst::AtomicSetPacketHeader(
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(HSA_PACKET_TYPE_KERNEL_DISPATCH << HSA_PACKET_HEADER_TYPE) |
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(1 << HSA_PACKET_HEADER_BARRIER),
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aql().setup,
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reinterpret_cast<hsa_kernel_dispatch_packet_t *>
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(&(q_base_addr)[index[num_of_pkts_ - 1] & queue_mask]));
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// Set packet header reversly; set all headers except the very first
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// one, for now.
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for (int32_t j = num_of_pkts_ - 1; j >= 0; j--) {
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rocrtst::AtomicSetPacketHeader(
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HSA_PACKET_TYPE_KERNEL_DISPATCH << HSA_PACKET_HEADER_TYPE,
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aql().setup,
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reinterpret_cast<hsa_kernel_dispatch_packet_t *>
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(&(q_base_addr)[index[j] & queue_mask]));
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}
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p_timer.StopTimer(id);
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timer.push_back(p_timer.ReadTimer(id));
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for (uint32_t j = 0; j < num_of_pkts_; j++) {
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hsa_signal_store_screlease(main_queue()->doorbell_signal, index[j]);
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}
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// Wait on the dispatch signal until the kernel is finished.
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while (hsa_signal_wait_scacquire(aql().completion_signal,
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HSA_SIGNAL_CONDITION_EQ, 0, UINT64_MAX, HSA_WAIT_STATE_ACTIVE) != 0) {
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}
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hsa_signal_store_screlease(aql().completion_signal, 1);
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free(index);
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if (verbosity() >= VERBOSE_PROGRESS) {
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std::cout << ".";
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fflush(stdout);
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}
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}
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std::cout << std::endl;
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// Abandon the first result and after sort, delete the last 2% value
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timer.erase(timer.begin());
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std::sort(timer.begin(), timer.end());
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timer.erase(timer.begin() + num_iteration(), timer.end());
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enqueue_time_mean_ = rocrtst::CalcMean(timer);
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return;
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}
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void EnqueueLatency::DisplayTestInfo(void) {
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TestBase::DisplayTestInfo();
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}
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void EnqueueLatency::DisplayResults(void) const {
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if (!rocrtst::CheckProfile(this)) {
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return;
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}
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TestBase::DisplayResults();
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std::cout << "Average Time to Completion: ";
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if (enqueue_single_) {
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std::cout << enqueue_time_mean_ * 1e6;
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} else {
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std::cout << enqueue_time_mean_ * 1e6 / num_of_pkts_;
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}
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std::cout << " uS" << std::endl;
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return;
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}
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void EnqueueLatency::Close() {
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TestBase::Close();
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return;
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}
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