Wenkai Du
390 lines
17 KiB
C++
390 lines
17 KiB
C++
/*************************************************************************
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* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
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* Modifications Copyright (c) 2019-2022 Advanced Micro Devices, Inc. All rights reserved.
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*
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* See LICENSE.txt for license information
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************************************************************************/
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#include "device.h"
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#include "collectives.h"
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#include "primitives.h"
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namespace {
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template<typename T, typename RedOp, typename Proto>
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#if defined(USE_INDIRECT_FUNCTION_CALL) && !defined(__gfx940__) && !defined(__gfx941__) && !defined(__gfx942__) && !defined(__gfx950__)
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__device__ void runRing(int tid, int nthreads, struct ncclDevWorkColl* work) {
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#else
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__device__ __attribute__((noinline)) void runRing(int tid, int nthreads, struct ncclDevWorkColl* work) {
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#endif
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ncclRing *ring = &ncclShmem.channel.ring;
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int const *ringRanks = ring->userRanks;
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const int nranks = ncclShmem.comm.nRanks;
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size_t count;
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size_t gridOffset;
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size_t channelCount;
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size_t chunkCount;
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ncclCollCbdPart(work, ncclShmem.channelId, Proto::Id, sizeof(T), &count, &gridOffset, &channelCount, &chunkCount);
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size_t offset;
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size_t dataOffset;
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uint32_t nelem;
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int rankDest;
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#if defined(ENABLE_NPKIT)
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int npKitCtxIdx = ncclShmem.channelId;
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#endif
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_TIME_SYNC_CPU)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_TIME_SYNC_CPU, 0, 0, NPKIT_GET_CPU_TIMESTAMP_FROM_BLOCK,
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_TIME_SYNC_GPU)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_TIME_SYNC_GPU, 0, 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_ENTRY)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_ENTRY, count*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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Primitives<T, RedOp, FanSymmetric<1>, 0, Proto, 0>
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prims(tid, nthreads, &ring->prev, &ring->next, work->sendbuff, work->recvbuff, work->redOpArg, 0, work->connIndex, work->connIndex);
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#if defined(ENABLE_NPKIT)
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if (tid == 0) {
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prims.npKitCtxIdx = npKitCtxIdx;
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}
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#endif
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for (size_t elemOffset = 0; elemOffset < channelCount; elemOffset += chunkCount) {
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nelem = min(chunkCount, channelCount - elemOffset);
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dataOffset = gridOffset + elemOffset;
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/////////////// begin ReduceScatter steps ///////////////
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// step 0: push data to next GPU
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_SEND_ENTRY)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_SEND_ENTRY, nelem*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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rankDest = ringRanks[nranks-1];
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offset = dataOffset + rankDest * count;
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prims.send(offset, nelem);
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_SEND_EXIT)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_SEND_EXIT, nelem*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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// k-2 steps: reduce and copy to next GPU
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_SEND_ENTRY)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_SEND_ENTRY, nelem*(nranks-2)*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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for (int j=2; j<nranks; ++j) {
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rankDest = ringRanks[nranks-j];
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offset = dataOffset + rankDest * count;
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prims.recvReduceSend(offset, nelem);
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}
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_SEND_EXIT)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_SEND_EXIT, nelem*(nranks-2)*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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// step k-1: reduce this buffer and data, which will produce the final result
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_COPY_ENTRY)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_COPY_ENTRY, nelem*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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rankDest = ringRanks[0];
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offset = dataOffset + rankDest * count;
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prims.recvReduceCopy(offset, dataOffset, nelem, /*postOp=*/true);
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_COPY_EXIT)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_RECV_REDUCE_COPY_EXIT, nelem*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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}
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#if defined(ENABLE_NPKIT) && defined(ENABLE_NPKIT_EVENT_REDUCE_SCATTER_RING_EXIT)
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if (tid == 0) {
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NpKit::CollectGpuEvent(NPKIT_EVENT_REDUCE_SCATTER_RING_EXIT, count*sizeof(T), 0, NPKIT_GET_GPU_TIMESTAMP(),
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ncclShmem.comm.npKitEventCollectContexts + npKitCtxIdx);
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}
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#endif
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}
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}
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template<typename T, typename RedOp>
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struct RunWorkColl<ncclFuncReduceScatter, T, RedOp, NCCL_ALGO_RING, NCCL_PROTO_SIMPLE> {
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__device__ __forceinline__ void run(int tid, int nthreads, struct ncclDevWorkColl* work) {
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using Proto = ProtoSimple<REDUCESCATTER_CHUNKSTEPS/REDUCESCATTER_SLICESTEPS, REDUCESCATTER_SLICESTEPS>;
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runRing<T, RedOp, Proto>(tid, nthreads, work);
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}
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};
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template<typename T, typename RedOp>
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struct RunWorkColl<ncclFuncReduceScatter, T, RedOp, NCCL_ALGO_RING, NCCL_PROTO_LL> {
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__device__ __forceinline__ void run(int tid, int nthreads, struct ncclDevWorkColl* work) {
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runRing<T, RedOp, ProtoLL>(tid, nthreads, work);
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}
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};
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template<typename T, typename RedOp>
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struct RunWorkColl<ncclFuncReduceScatter, T, RedOp, NCCL_ALGO_RING, NCCL_PROTO_LL128> {
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__device__ __forceinline__ void run(int tid, int nthreads, struct ncclDevWorkColl* work) {
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runRing<T, RedOp, ProtoLL128>(tid, nthreads, work);
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}
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};
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template<typename T, typename RedOp>
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struct RunWorkColl<ncclFuncReduceScatter, T, RedOp, NCCL_ALGO_NVLS, NCCL_PROTO_SIMPLE> {
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__device__ __forceinline__ void run(int tid, int/*nthreads*/, struct ncclDevWorkColl* work) {
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struct ncclNvls* nvls = &ncclShmem.channel.nvls;
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size_t count;
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size_t gridOffset;
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size_t channelCount;
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size_t chunkCount;
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ncclCollCbdPart(work, ncclShmem.channelId, NCCL_PROTO_SIMPLE, sizeof(T), &count, &gridOffset, &channelCount, &chunkCount);
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const int rank = ncclShmem.comm.rank;
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const int nranks = ncclShmem.comm.nRanks;
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size_t offset;
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int nelem;
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/* if we are direct NVLS, we only need to allocate 1 warp to scatter for sync;
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* if not, based on #ranks, we allocate 7 or 5 warps to reduce to saturate bandwidth
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* and the rest are allocated to scatter. */
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const int nThreadsReduce = work->regUsed ? (NCCL_MAX_NTHREADS - WARP_SIZE) : (nranks <= 6 ? 7 * WARP_SIZE : 5 * WARP_SIZE);
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const int nThreadsScatter = work->regUsed ? WARP_SIZE : (NCCL_MAX_NTHREADS - nThreadsReduce);
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const int tidEndScatter = nThreadsScatter;
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const int tidEndReduce = tidEndScatter + nThreadsReduce;
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if (!work->regUsed) {
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if (tid < tidEndScatter) {
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// Scatter
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using Proto = ProtoSimple<1, 1, COLL_UNROLL>;
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Primitives<T, RedOp, FanAsymmetric<0, NCCL_MAX_NVLS_ARITY>, /*Direct=*/0, Proto, 0>
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prims(tid, nThreadsScatter, NULL, nvls->up, work->sendbuff, NULL,
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work->redOpArg, 0 * Proto::MaxGroupWidth, 1, 1);
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for (size_t elemOffset = 0; elemOffset < channelCount; elemOffset += chunkCount) {
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offset = gridOffset + elemOffset;
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nelem = min(chunkCount, channelCount - elemOffset);
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prims.scatter(offset, nvls->nHeads * count, nelem, count, -1, 0);
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}
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} else if (tid < tidEndReduce) {
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// Reduce through NVLS
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using Proto = ProtoSimple<1, 1, COLL_UNROLL, 1, 0>;
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Primitives<T, RedOp, FanAsymmetric<1, 0>, /*Direct=*/0, Proto, 0>
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prims(tid - tidEndScatter, nThreadsReduce, &nvls->down, NULL, NULL, work->recvbuff,
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work->redOpArg, 3 * Proto::MaxGroupWidth, 0, 0);
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for (size_t elemOffset = 0; elemOffset < channelCount; elemOffset += chunkCount) {
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offset = gridOffset + elemOffset;
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nelem = min(chunkCount, channelCount - elemOffset);
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prims.recv(offset, nelem);
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}
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}
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} else {
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if (tid < tidEndScatter) {
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// Scatter
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using Proto = ProtoSimple<1, 1, COLL_UNROLL>;
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Primitives<T, RedOp, FanSymmetric<NCCL_MAX_NVLS_ARITY>, /*Direct=*/0, Proto, 0>
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prims(tid, nThreadsScatter, nvls->up, nvls->up, NULL, NULL,
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work->redOpArg, 0 * Proto::MaxGroupWidth, 1, 1);
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for (size_t elemOffset = 0; elemOffset < channelCount; elemOffset += chunkCount) {
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prims.scatter(0, 0, 0, 0, -1, 0);
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}
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/* gather used as sync */
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prims.gather(0, 0, 0, 0, -1, 0);
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} else if (tid < tidEndReduce) {
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// Reduce through NVLS
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using Proto = ProtoSimple<1, 1, COLL_UNROLL, 1, 0>;
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Primitives<T, RedOp, FanSymmetric<1>, /*Direct=*/1, Proto, 0>
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prims(tid - tidEndScatter, nThreadsReduce, &nvls->down, &nvls->down, NULL, work->recvbuff,
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work->redOpArg, 3 * Proto::MaxGroupWidth, 0, 0, work);
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for (size_t elemOffset = 0; elemOffset < channelCount; elemOffset += chunkCount) {
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size_t outOffset = gridOffset + elemOffset;
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size_t inpOffset = outOffset + rank * count;
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nelem = min(chunkCount, channelCount - elemOffset);
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prims.directRecvCopy(inpOffset, outOffset, nelem);
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}
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/* send for sync */
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prims.send(0, 0);
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}
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}
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}
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};
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template<typename T, typename RedOp>
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struct RunWorkColl<ncclFuncReduceScatter, T, RedOp, NCCL_ALGO_COLLNET_DIRECT, NCCL_PROTO_SIMPLE> {
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template<bool ReduceSendNotRecv>
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struct Scatterer {
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struct ncclDevWorkColl* work;
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int chunkSize;
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ssize_t railGridOffset;
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template<int SlicePerChunk, int MinSrcs, int MaxSrcs, int MinDsts, int MaxDsts>
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__device__ __forceinline__ void operator()(
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int tid, int tn, int slice, int maxSliceSize,
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int nSrcs, void** srcPtrs, int nDsts, void** dstPtrs, int32_t* dstSizes
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) {
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static_assert(SlicePerChunk==1, "require: SlicePerChunk==1");
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static_assert(MaxDsts<=1 || MaxSrcs<=1, "require: MaxDsts<=1 || MaxSrcs<=1");
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struct ncclDirect* direct = &ncclShmem.channel.collnetDirect;
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int nNodes = ncclShmem.comm.nNodes;
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int nRails = direct->nHeads;
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int part = ncclShmem.channelId - work->channelLo;
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void* inbuf = (void*)work->sendbuff;
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ssize_t sizePerRank = work->collnet.count;
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ssize_t railAllBeg = min(railGridOffset + part*chunkSize, nNodes*sizePerRank);
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ssize_t railAllEnd = min(railAllBeg + chunkSize, nNodes*sizePerRank);
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int railAllSize = railAllEnd - railAllBeg;
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if (tid < nDsts) dstSizes[tid] = railAllSize;
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int dst = 0;
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int rail;
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if (!ReduceSendNotRecv) {
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rail = direct->headRank;
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} else {
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rail = direct->headRank+1;
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if (rail == nRails) rail = 0;
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}
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do {
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int node = railAllBeg/sizePerRank;
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int railAllOffset = 0;
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while (railAllOffset < railAllSize) {
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ssize_t railOneBeg = node*sizePerRank;
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ssize_t railOneEnd = railOneBeg + sizePerRank;
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ssize_t railOneOffset = (railAllBeg+railAllOffset) - railOneBeg;
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int delta = min(railAllEnd, railOneEnd) - (railAllBeg+railAllOffset);
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int rank = ncclShmem.comm.collNetDenseToUserRank[node*nRails + rail];
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ssize_t userOneBeg = rank*sizePerRank + railOneOffset;
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reduceCopy<ncclCollUnroll(), RedOp, T,
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/*MultimemSrcs=*/0, 1+MinSrcs, 1+MaxSrcs,
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/*MultimemDsts,MinDsts,MaxDsts=*/0,1,1,
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/*PreOpSrcs=*/1>
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(tid, tn, work->redOpArg, &work->redOpArg, false,
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/*nSrcs=*/1+nSrcs, [=]__device__(int s) {
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return s==0 ? (T*)inbuf + userOneBeg
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: (T*)srcPtrs[s-1] + railAllOffset;
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},
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/*nDsts=*/1, [=]__device__(int d/*==0*/) {
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return (T*)dstPtrs[dst] + railAllOffset;
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},
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delta);
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railAllOffset += delta;
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node += 1;
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}
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dst += 1;
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rail += 1;
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if (rail == nRails) rail = 0;
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} while (ReduceSendNotRecv && dst < nRails-1);
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}
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};
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__device__ __forceinline__ void run(int tid, int nthreads, struct ncclDevWorkColl* work) {
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const int part = ncclShmem.channelId - work->channelLo;
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const int nChannels = work->channelHi - work->channelLo + 1;
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struct ncclDirect* direct = &ncclShmem.channel.collnetDirect;
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int const &nNodes = ncclShmem.comm.nNodes;
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ssize_t chunkSize = int(work->collnet.chunkCount);
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ssize_t sizePerRank = work->collnet.count;
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// if (direct->out == -1) __trap();
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bool isMultiRail = (direct->nHeads > 1);
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int nWarps1 = (isMultiRail ? 2 : 0);
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int nWarps2 = (isMultiRail ? 2 : 1);
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int nWarps3 = 1;
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float denom = float(work->nWarps)/float(nWarps1+nWarps2+nWarps3);
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nWarps3 = int(denom*nWarps3);
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nWarps2 = int(denom*nWarps2);
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nWarps1 = work->nWarps - (nWarps2+nWarps3);
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using Proto = ProtoSimple<1, 1>;
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int tn = nWarps1*WARP_SIZE;
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if (tid < tn) {
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// Phase 1: Scatter inputs to peers
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Primitives<T, RedOp, FanAsymmetric<0, NCCL_MAX_DIRECT_ARITY>, /*Direct=*/0, Proto, 0>
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prims(tid, tn, nullptr, direct->heads+1, nullptr, nullptr,
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work->redOpArg, 0*Proto::MaxGroupWidth, 1, 1);
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for (ssize_t railGridOffset=0; railGridOffset < nNodes*sizePerRank; railGridOffset += nChannels*chunkSize) {
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Scatterer</*ReduceSendNotRecv=*/true> scat;
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scat.work = work;
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scat.chunkSize = chunkSize;
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scat.railGridOffset = railGridOffset;
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prims.template process</*Recv=*/0, /*Send=*/1>(scat);
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}
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return;
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}
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tid -= tn;
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tn = nWarps2*WARP_SIZE;
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if (tid < tn) {
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if (work->regUsed == NCCL_COLLNET_REG_BUFFER) {
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if (tid == 0) {
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int steps = (int)divUp(nNodes * sizePerRank * sizeof(T), NCCL_MAX_COLLNET_SIZE);
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Primitives<T, RedOp, FanAsymmetric<NCCL_MAX_DIRECT_ARITY, 1>, /*Direct=*/0, Proto, 0>::sendPeerNotify(direct->out, 1, steps);
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}
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__syncwarp();
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} else {
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// Phase 2: Reduce from peers + local input -> send to network
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Primitives<T, RedOp, FanAsymmetric<NCCL_MAX_DIRECT_ARITY, 1>, /*Direct=*/0, Proto, 0>
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prims(tid, tn, direct->heads + 1, &direct->out, nullptr, nullptr,
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work->redOpArg, 1 * Proto::MaxGroupWidth, 1, 1);
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for (ssize_t railGridOffset = 0; railGridOffset < nNodes * sizePerRank; railGridOffset += nChannels * chunkSize) {
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Scatterer</*ReduceSendNotRecv=*/false> scat;
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scat.work = work;
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scat.chunkSize = chunkSize;
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scat.railGridOffset = railGridOffset;
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prims.template process</*Recv=*/1, /*Send=*/1>(scat);
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}
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}
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return;
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}
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tid -= tn;
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tn = nWarps3*WARP_SIZE;
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if (tid < tn) {
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if (work->regUsed == NCCL_COLLNET_REG_BUFFER) {
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if (tid == 0) {
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int steps = (int)divUp(nNodes * sizePerRank * sizeof(T), NCCL_MAX_COLLNET_SIZE);
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Primitives<T, RedOp, FanAsymmetric<1, 0>, /*Direct=*/0, Proto, 0>::recvPeerNotify(direct->out, 0, steps);
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}
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__syncwarp();
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} else {
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// Phase 3: recv from network
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Primitives<T, RedOp, FanAsymmetric<1, 0>, /*Direct=*/0, Proto, 0>
|
|
prims(tid, tn, &direct->out, nullptr, nullptr, work->recvbuff,
|
|
work->redOpArg, 2 * Proto::MaxGroupWidth, 0, 0);
|
|
for (ssize_t railGridOffset = 0; railGridOffset < nNodes * sizePerRank; railGridOffset += nChannels * chunkSize) {
|
|
ssize_t railAllBeg = railGridOffset + part * chunkSize;
|
|
ssize_t railAllEnd = min(railAllBeg + chunkSize, nNodes * sizePerRank);
|
|
ssize_t railOneBeg = ncclShmem.comm.node * sizePerRank;
|
|
ssize_t railOneEnd = railOneBeg + sizePerRank;
|
|
ssize_t beg = max(railAllBeg, railOneBeg);
|
|
ssize_t end = min(railAllEnd, railOneEnd);
|
|
prims.recv(beg - railOneBeg, max(ssize_t(0), end - beg), /*postOp=*/true);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
}; |