Tony Gutierrez
6e3c375bf1
This builds on a prior change that allowed for allocating a user-mode queue's packet buffer in device memory to also allocate the queue struct in device memory. This provides additional latency benefits particularly for cases where dispatches are performed from the GPU itself. Flags are added to support the various use cases.
481 lines
17 KiB
C++
481 lines
17 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2024, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIESd OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef HSA_RUNTIME_CORE_INC_FLAG_H_
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#define HSA_RUNTIME_CORE_INC_FLAG_H_
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#include <stdint.h>
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#include <vector>
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#include <map>
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#include <string>
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#include "core/util/os.h"
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#include "core/util/utils.h"
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namespace rocr {
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class Flag {
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public:
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enum SDMA_OVERRIDE { SDMA_DISABLE, SDMA_ENABLE, SDMA_DEFAULT };
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enum SRAMECC_ENABLE { SRAMECC_DISABLED, SRAMECC_ENABLED, SRAMECC_DEFAULT };
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// The values are meaningful and chosen to satisfy the thunk API.
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enum XNACK_REQUEST { XNACK_DISABLE = 0, XNACK_ENABLE = 1, XNACK_UNCHANGED = 2 };
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static_assert(XNACK_DISABLE == 0, "XNACK_REQUEST enum values improperly changed.");
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static_assert(XNACK_ENABLE == 1, "XNACK_REQUEST enum values improperly changed.");
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// Lift limit for 2.10 release RCCL workaround. This limit is not used when asynchronous scratch
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// reclaim is supported
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const size_t DEFAULT_SCRATCH_SINGLE_LIMIT = (140 * (1UL<<20)); // small_limit >> 2;
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const size_t DEFAULT_SCRATCH_SINGLE_LIMIT_ASYNC_PER_XCC = (3 * (1UL<<30)); // 3 GB
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const size_t DEFAULT_PCS_MAX_DEVICE_BUFFER_SIZE = (256 * (1UL<<20)); //256 MB
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Flag() {}
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virtual ~Flag() {}
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void Refresh() {
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std::string var = os::GetEnvVar("HSA_CHECK_FLAT_SCRATCH");
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check_flat_scratch_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_ENABLE_VM_FAULT_MESSAGE");
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enable_vm_fault_message_ = (var == "0") ? false : true;
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var = os::GetEnvVar("HSA_ENABLE_QUEUE_FAULT_MESSAGE");
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enable_queue_fault_message_ = (var == "0") ? false : true;
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var = os::GetEnvVar("HSA_ENABLE_INTERRUPT");
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enable_interrupt_ = (var == "0") ? false : true;
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var = os::GetEnvVar("HSA_ENABLE_SDMA");
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enable_sdma_ = (var == "0") ? SDMA_DISABLE : ((var == "1") ? SDMA_ENABLE : SDMA_DEFAULT);
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var = os::GetEnvVar("HSA_ENABLE_PEER_SDMA");
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enable_peer_sdma_ = (var == "0") ? SDMA_DISABLE : ((var == "1") ? SDMA_ENABLE : SDMA_DEFAULT);
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var = os::GetEnvVar("HSA_ENABLE_SDMA_GANG");
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enable_sdma_gang_ = (var == "0") ? SDMA_DISABLE :
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((var == "1") ? SDMA_ENABLE : SDMA_DEFAULT);
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if (enable_sdma_ == SDMA_DISABLE) enable_sdma_gang_ = SDMA_DISABLE;
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var = os::GetEnvVar("HSA_ENABLE_SDMA_COPY_SIZE_OVERRIDE");
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enable_sdma_copy_size_override_ = (var == "0") ? SDMA_DISABLE :
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((var == "1") ? SDMA_ENABLE : SDMA_DEFAULT);
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var = os::GetEnvVar("HSA_ENABLE_SDMA_RECOMMENDED_ENG");
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enable_sdma_recommended_eng_ = (var == "0") ? SDMA_DISABLE :
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((var == "1") ? SDMA_ENABLE : SDMA_DEFAULT);
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visible_gpus_ = os::GetEnvVar("ROCR_VISIBLE_DEVICES");
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filter_visible_gpus_ = os::IsEnvVarSet("ROCR_VISIBLE_DEVICES");
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var = os::GetEnvVar("HSA_RUNNING_UNDER_VALGRIND");
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running_valgrind_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_SDMA_WAIT_IDLE");
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sdma_wait_idle_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_MAX_QUEUES");
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max_queues_ = static_cast<uint32_t>(atoi(var.c_str()));
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// Maximum amount of scratch mem that can be used per process per gpu
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var = os::GetEnvVar("HSA_SCRATCH_MEM");
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scratch_mem_size_ = atoi(var.c_str());
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// Scratch memory sizes > HSA_SCRATCH_SINGLE_LIMIT will trigger a use-once scheme
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// We also reserve HSA_SCRATCH_SINGLE_LIMIT per process per gpu to guarrantee we
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// have sufficient memory to for scratch in case user tried to allocate all device
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// memory
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if (os::IsEnvVarSet("HSA_SCRATCH_SINGLE_LIMIT")) {
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var = os::GetEnvVar("HSA_SCRATCH_SINGLE_LIMIT");
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char* end;
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scratch_single_limit_ = strtoul(var.c_str(), &end, 10);
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} else {
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scratch_single_limit_ = DEFAULT_SCRATCH_SINGLE_LIMIT;
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}
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// On GPUs that support asynchronous scratch reclaim
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// Scratch memory sizes > HSA_SCRATCH_SINGLE_LIMIT_ASYNC will trigger a use-once scheme
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// Note: This only sets the initial value for the threshold. If
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// hsa_amd_agent_set_async_scratch_limit is called after initialization, the threshold
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// will be updated.
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if (os::IsEnvVarSet("HSA_SCRATCH_SINGLE_LIMIT_ASYNC")) {
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var = os::GetEnvVar("HSA_SCRATCH_SINGLE_LIMIT_ASYNC");
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char* end;
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scratch_single_limit_async_ = strtoul(var.c_str(), &end, 10);
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} else {
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scratch_single_limit_async_ = 0; // DEFAULT_SCRATCH_SINGLE_LIMIT_ASYNC_PER_XCC;
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}
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// On GPUs that support asynchronous scratch reclaim this can be used to disable this feature.
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// Disabling asynchronous scratch reclaim also disables use of alternate scratch
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// HSA_ENABLE_SCRATCH_ALT
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var = os::GetEnvVar("HSA_ENABLE_SCRATCH_ASYNC_RECLAIM");
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enable_scratch_async_reclaim_ = (var == "0") ? false : true;
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var = os::GetEnvVar("HSA_ENABLE_SCRATCH_ALT");
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// Temporary: Completely disable alternate scratch because we need to update
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// the debugger so that it can tell whether a dispatch is using alternate scratch
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// instead of main scratch
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// enable_scratch_alt_ = (var == "0") || !enable_scratch_async_reclaim_ ? false : true;
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enable_scratch_alt_ = false;
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tools_lib_names_ = os::GetEnvVar("HSA_TOOLS_LIB");
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var = os::GetEnvVar("HSA_TOOLS_REPORT_LOAD_FAILURE");
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ifdebug {
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report_tool_load_failures_ = (var == "1") ? true : false;
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} else {
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report_tool_load_failures_ = (var == "0") ? false : true;
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}
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var = os::GetEnvVar("HSA_TOOLS_DISABLE_REGISTER");
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disable_tool_register_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_TOOLS_REPORT_REGISTER_FAILURE");
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report_tool_register_failures_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_DISABLE_FRAGMENT_ALLOCATOR");
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disable_fragment_alloc_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_ENABLE_SDMA_HDP_FLUSH");
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enable_sdma_hdp_flush_ = (var == "0") ? false : true;
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var = os::GetEnvVar("HSA_REV_COPY_DIR");
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rev_copy_dir_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_FORCE_FINE_GRAIN_PCIE");
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fine_grain_pcie_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_NO_SCRATCH_RECLAIM");
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no_scratch_reclaim_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_NO_SCRATCH_THREAD_LIMITER");
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no_scratch_thread_limit_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_DISABLE_IMAGE");
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disable_image_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_DISABLE_PC_SAMPLING");
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disable_pc_sampling_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_LOADER_ENABLE_MMAP_URI");
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loader_enable_mmap_uri_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_FORCE_SDMA_SIZE");
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force_sdma_size_ = var.empty() ? 1024 * 1024 : atoi(var.c_str());
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var = os::GetEnvVar("HSA_IGNORE_SRAMECC_MISREPORT");
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check_sramecc_validity_ = (var == "1") ? false : true;
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// Legal values are zero "0" or one "1". Any other value will
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// be interpreted as not defining the env variable.
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var = os::GetEnvVar("HSA_XNACK");
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xnack_ = (var == "0") ? XNACK_DISABLE : ((var == "1") ? XNACK_ENABLE : XNACK_UNCHANGED);
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var = os::GetEnvVar("HSA_ENABLE_DEBUG");
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debug_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_CU_MASK_SKIP_INIT");
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cu_mask_skip_init_ = (var == "1") ? true : false;
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// Temporary opt-in for corrected HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT behavior.
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// Will become opt-out and possibly removed in future releases.
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var = os::GetEnvVar("HSA_COOP_CU_COUNT");
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coop_cu_count_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_DISCOVER_COPY_AGENTS");
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discover_copy_agents_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_SVM_PROFILE");
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svm_profile_ = var;
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var = os::GetEnvVar("HSA_ENABLE_SRAMECC");
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sramecc_enable_ =
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(var == "0") ? SRAMECC_DISABLED : ((var == "1") ? SRAMECC_ENABLED : SRAMECC_DEFAULT);
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var = os::GetEnvVar("HSA_IMAGE_PRINT_SRD");
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image_print_srd_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_ENABLE_MWAITX");
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enable_mwaitx_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_ENABLE_IPC_MODE_LEGACY");
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enable_ipc_mode_legacy_ = (var == "0") ? false : true; // Legacy mode by default
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if (os::IsEnvVarSet("HSA_PCS_MAX_DEVICE_BUFFER_SIZE")) {
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var = os::GetEnvVar("HSA_PCS_MAX_DEVICE_BUFFER_SIZE");
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char* end;
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pc_sampling_max_device_buffer_size_ = strtoul(var.c_str(), &end, 10);
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} else {
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pc_sampling_max_device_buffer_size_ = DEFAULT_PCS_MAX_DEVICE_BUFFER_SIZE;
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}
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// Temporary environment variable to disable CPU affinity override
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// Will either rename to HSA_OVERRIDE_CPU_AFFINITY later or remove completely.
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var = os::GetEnvVar("HSA_OVERRIDE_CPU_AFFINITY_DEBUG");
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override_cpu_affinity_ = (var == "0") ? false : true;
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var = os::GetEnvVar("HSA_ALLOCATE_QUEUE_DEV_MEM");
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dev_mem_queue_buf_ = (var == "1") ? true : false;
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var = os::GetEnvVar("HSA_WAIT_ANY_DEBUG");
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wait_any_ = (var == "1") ? true : false;
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/* hsa_signal_wait_relaxed abort timeout */
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var = os::GetEnvVar("HSA_SIGNAL_WAIT_ABORT_TIMEOUT");
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signal_abort_timeout_ = var.empty() ? 0 : atoi(var.c_str());
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/* Valid inputs are 0-99, HIGH, MAX */
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var = os::GetEnvVar("HSA_ASYNCEVENTS_THREAD_PRIORITY");
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async_events_thread_priority_ = os::OS_THREAD_PRIORITY_DEFAULT;
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if (var == "MAX") {
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async_events_thread_priority_ = os::OS_THREAD_PRIORITY_MAX;
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} else if (var == "HIGH") {
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async_events_thread_priority_ = os::OS_THREAD_PRIORITY_HIGH;
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} else if (var != "") {
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char* end;
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int input = strtol(var.c_str(), &end, 10);
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if (input >= 0 && input <= 99)
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async_events_thread_priority_ = input;
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else
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fprintf(stderr, "Failed to parse HSA_ASYNCEVENTS_THREAD_PRIORITY");
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}
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var = os::GetEnvVar("HSA_IMAGE_ENABLE_3D_SWIZZLE_DEBUG");
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enable_3d_swizzle_ = (var == "1") ? true : false;
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}
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void parse_masks(uint32_t maxGpu, uint32_t maxCU) {
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std::string var = os::GetEnvVar("HSA_CU_MASK");
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parse_masks(var, maxGpu, maxCU);
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}
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bool wait_any() const { return wait_any_; }
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bool check_flat_scratch() const { return check_flat_scratch_; }
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bool enable_vm_fault_message() const { return enable_vm_fault_message_; }
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bool enable_queue_fault_message() const { return enable_queue_fault_message_; }
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bool enable_interrupt() const { return enable_interrupt_; }
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bool enable_sdma_hdp_flush() const { return enable_sdma_hdp_flush_; }
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bool running_valgrind() const { return running_valgrind_; }
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bool sdma_wait_idle() const { return sdma_wait_idle_; }
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bool report_tool_load_failures() const { return report_tool_load_failures_; }
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bool report_tool_register_failures() const { return report_tool_register_failures_; }
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bool disable_tool_register() const { return disable_tool_register_; }
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bool disable_fragment_alloc() const { return disable_fragment_alloc_; }
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bool rev_copy_dir() const { return rev_copy_dir_; }
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bool fine_grain_pcie() const { return fine_grain_pcie_; }
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bool no_scratch_reclaim() const { return no_scratch_reclaim_; }
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bool no_scratch_thread_limiter() const { return no_scratch_thread_limit_; }
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SDMA_OVERRIDE enable_sdma() const { return enable_sdma_; }
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SDMA_OVERRIDE enable_peer_sdma() const { return enable_peer_sdma_; }
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SDMA_OVERRIDE enable_sdma_gang() const { return enable_sdma_gang_; }
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SDMA_OVERRIDE enable_sdma_copy_size_override() const { return enable_sdma_copy_size_override_; }
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SDMA_OVERRIDE enable_sdma_recommended_eng() const { return enable_sdma_recommended_eng_; }
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std::string visible_gpus() const { return visible_gpus_; }
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bool filter_visible_gpus() const { return filter_visible_gpus_; }
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uint32_t max_queues() const { return max_queues_; }
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size_t scratch_mem_size() const { return scratch_mem_size_; }
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size_t scratch_single_limit() const { return scratch_single_limit_; }
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bool enable_scratch_async_reclaim() const { return enable_scratch_async_reclaim_; }
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bool enable_scratch_alt() const { return enable_scratch_alt_; }
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size_t scratch_single_limit_async() const { return scratch_single_limit_async_; }
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std::string tools_lib_names() const { return tools_lib_names_; }
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bool disable_image() const { return disable_image_; }
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bool disable_pc_sampling() const { return disable_pc_sampling_; }
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bool loader_enable_mmap_uri() const { return loader_enable_mmap_uri_; }
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size_t force_sdma_size() const { return force_sdma_size_; }
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bool check_sramecc_validity() const { return check_sramecc_validity_; }
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bool override_cpu_affinity() const { return override_cpu_affinity_; }
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bool image_print_srd() const { return image_print_srd_; }
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bool check_mwaitx(bool mwaitx_supported) {
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if (enable_mwaitx_ && !mwaitx_supported) enable_mwaitx_ = false;
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return enable_mwaitx_;
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}
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XNACK_REQUEST xnack() const { return xnack_; }
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bool debug() const { return debug_; }
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const std::vector<uint32_t>& cu_mask(uint32_t gpu_index) const {
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static const std::vector<uint32_t> empty;
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auto it = cu_mask_.find(gpu_index);
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if (it == cu_mask_.end()) return empty;
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return it->second;
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}
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bool cu_mask_skip_init() const { return cu_mask_skip_init_; }
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bool coop_cu_count() const { return coop_cu_count_; }
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bool discover_copy_agents() const { return discover_copy_agents_; }
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const std::string& svm_profile() const { return svm_profile_; }
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SRAMECC_ENABLE sramecc_enable() const { return sramecc_enable_; }
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bool enable_ipc_mode_legacy() const { return enable_ipc_mode_legacy_; }
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size_t pc_sampling_max_device_buffer_size() const { return pc_sampling_max_device_buffer_size_; }
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bool dev_mem_queue_buf() const { return dev_mem_queue_buf_; }
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uint32_t signal_abort_timeout() const { return signal_abort_timeout_; }
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int async_events_thread_priority() const { return async_events_thread_priority_; }
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bool enable_3d_swizzle() const { return enable_3d_swizzle_; }
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private:
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bool check_flat_scratch_;
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bool enable_vm_fault_message_;
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bool enable_interrupt_;
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bool enable_sdma_hdp_flush_;
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bool running_valgrind_;
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bool sdma_wait_idle_;
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bool enable_queue_fault_message_;
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bool report_tool_load_failures_;
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bool report_tool_register_failures_ = false;
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bool disable_tool_register_ = false;
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bool disable_fragment_alloc_;
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bool rev_copy_dir_;
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bool fine_grain_pcie_;
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bool no_scratch_reclaim_;
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bool no_scratch_thread_limit_;
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bool disable_image_;
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bool disable_pc_sampling_;
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bool loader_enable_mmap_uri_;
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bool check_sramecc_validity_;
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bool debug_;
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bool cu_mask_skip_init_;
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bool coop_cu_count_;
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bool discover_copy_agents_;
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bool override_cpu_affinity_;
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bool image_print_srd_;
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bool enable_mwaitx_;
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bool enable_ipc_mode_legacy_;
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bool wait_any_;
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bool dev_mem_queue_buf_;
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uint32_t signal_abort_timeout_;
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int async_events_thread_priority_;
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bool enable_3d_swizzle_ = false;
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SDMA_OVERRIDE enable_sdma_;
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SDMA_OVERRIDE enable_peer_sdma_;
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SDMA_OVERRIDE enable_sdma_gang_;
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SDMA_OVERRIDE enable_sdma_copy_size_override_;
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SDMA_OVERRIDE enable_sdma_recommended_eng_;
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bool filter_visible_gpus_;
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std::string visible_gpus_;
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uint32_t max_queues_;
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size_t scratch_mem_size_;
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size_t scratch_single_limit_;
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size_t scratch_single_limit_async_;
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bool enable_scratch_async_reclaim_;
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bool enable_scratch_alt_;
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std::string tools_lib_names_;
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std::string svm_profile_;
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size_t force_sdma_size_;
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// Indicates user preference for Xnack state.
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XNACK_REQUEST xnack_;
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SRAMECC_ENABLE sramecc_enable_;
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size_t pc_sampling_max_device_buffer_size_;
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// Map GPU index post RVD to its default cu mask.
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std::map<uint32_t, std::vector<uint32_t>> cu_mask_;
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void parse_masks(std::string& args, uint32_t maxGpu, uint32_t maxCU);
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DISALLOW_COPY_AND_ASSIGN(Flag);
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};
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} // namespace rocr
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#endif // header guard
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