David Yat Sin
ebc51dd0eb
Reverting this as current mainline compiler branch does not support
gfx1150/gfx1151 yet. Will bring back later.
This reverts commit e877840197.
Change-Id: I31ff4fb2d5817538094a7ffaeba96dd6a7d660c7
202 lines
7.7 KiB
C
202 lines
7.7 KiB
C
/*
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************************************************************************************************************************
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*
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* Copyright (C) 2017-2022 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE
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*
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***********************************************************************************************************************/
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#ifndef _AMDGPU_ASIC_ADDR_H
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#define _AMDGPU_ASIC_ADDR_H
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#define ATI_VENDOR_ID 0x1002
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#define AMD_VENDOR_ID 0x1022
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// AMDGPU_VENDOR_IS_AMD(vendorId)
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#define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID))
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#define FAMILY_UNKNOWN 0x00
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#define FAMILY_TN 0x69
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#define FAMILY_SI 0x6E
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#define FAMILY_CI 0x78
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#define FAMILY_KV 0x7D
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#define FAMILY_VI 0x82
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#define FAMILY_POLARIS 0x82
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#define FAMILY_CZ 0x87
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#define FAMILY_AI 0x8D
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#define FAMILY_RV 0x8E
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#define FAMILY_NV 0x8F
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#define FAMILY_VGH 0x90
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#define FAMILY_GFX1100 0x91
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#define FAMILY_GFX1103 0x94
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#define FAMILY_RMB 0x92
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#define FAMILY_GC_10_3_6 0x95
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#define FAMILY_GC_10_3_7 0x97
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// AMDGPU_FAMILY_IS(familyId, familyName)
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#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
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#define FAMILY_IS_TN(f) FAMILY_IS(f, TN)
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#define FAMILY_IS_SI(f) FAMILY_IS(f, SI)
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#define FAMILY_IS_CI(f) FAMILY_IS(f, CI)
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#define FAMILY_IS_KV(f) FAMILY_IS(f, KV)
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#define FAMILY_IS_VI(f) FAMILY_IS(f, VI)
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#define FAMILY_IS_POLARIS(f) FAMILY_IS(f, POLARIS)
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#define FAMILY_IS_CZ(f) FAMILY_IS(f, CZ)
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#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
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#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
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#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
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#define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB)
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#define FAMILY_IS_GFX1100(f) FAMILY_IS(f, GFX1100)
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#define FAMILY_IS_GFX1103(f) FAMILY_IS(f, GFX1103)
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#define AMDGPU_UNKNOWN 0xFF
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#define AMDGPU_TAHITI_RANGE 0x05, 0x14
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#define AMDGPU_PITCAIRN_RANGE 0x15, 0x28
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#define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C
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#define AMDGPU_OLAND_RANGE 0x3C, 0x46
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#define AMDGPU_HAINAN_RANGE 0x46, 0xFF
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#define AMDGPU_BONAIRE_RANGE 0x14, 0x28
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#define AMDGPU_HAWAII_RANGE 0x28, 0x3C
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#define AMDGPU_SPECTRE_RANGE 0x01, 0x41
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#define AMDGPU_SPOOKY_RANGE 0x41, 0x81
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#define AMDGPU_KALINDI_RANGE 0x81, 0xA1
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#define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF
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#define AMDGPU_ICELAND_RANGE 0x01, 0x14
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#define AMDGPU_TONGA_RANGE 0x14, 0x28
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#define AMDGPU_FIJI_RANGE 0x3C, 0x50
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#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A
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#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
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#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
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#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
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#define AMDGPU_CARRIZO_RANGE 0x01, 0x21
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#define AMDGPU_STONEY_RANGE 0x61, 0xFF
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#define AMDGPU_VEGA10_RANGE 0x01, 0x14
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#define AMDGPU_VEGA12_RANGE 0x14, 0x28
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#define AMDGPU_VEGA20_RANGE 0x28, 0x32
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#define AMDGPU_ARCTURUS_RANGE 0x32, 0x3C
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#define AMDGPU_ALDEBARAN_RANGE 0x3C, 0xFF
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#define AMDGPU_RAVEN_RANGE 0x01, 0x81
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#define AMDGPU_RAVEN2_RANGE 0x81, 0x91
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#define AMDGPU_RENOIR_RANGE 0x91, 0xFF
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#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
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#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
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#define AMDGPU_NAVI14_RANGE 0x14, 0x28
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#define AMDGPU_NAVI21_RANGE 0x28, 0x32
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#define AMDGPU_NAVI22_RANGE 0x32, 0x3C
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#define AMDGPU_NAVI23_RANGE 0x3C, 0x46
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#define AMDGPU_NAVI24_RANGE 0x46, 0x50
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#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF
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#define AMDGPU_GFX1100_RANGE 0x01, 0x10
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#define AMDGPU_GFX1101_RANGE 0x20, 0xFF
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#define AMDGPU_GFX1102_RANGE 0x10, 0x20
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#define AMDGPU_GFX1103_RANGE 0x01, 0xFF
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#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF
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#define AMDGPU_GFX1036_RANGE 0x01, 0xFF
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#define AMDGPU_GFX1037_RANGE 0x01, 0xFF
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#define AMDGPU_EXPAND_FIX(x) x
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#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
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#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
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// ASICREV_IS(eRevisionId, revisionName)
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#define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
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#define ASICREV_IS_TAHITI_P(r) ASICREV_IS(r, TAHITI)
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#define ASICREV_IS_PITCAIRN_PM(r) ASICREV_IS(r, PITCAIRN)
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#define ASICREV_IS_CAPEVERDE_M(r) ASICREV_IS(r, CAPEVERDE)
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#define ASICREV_IS_OLAND_M(r) ASICREV_IS(r, OLAND)
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#define ASICREV_IS_HAINAN_V(r) ASICREV_IS(r, HAINAN)
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#define ASICREV_IS_BONAIRE_M(r) ASICREV_IS(r, BONAIRE)
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#define ASICREV_IS_HAWAII_P(r) ASICREV_IS(r, HAWAII)
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#define ASICREV_IS_SPECTRE(r) ASICREV_IS(r, SPECTRE)
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#define ASICREV_IS_SPOOKY(r) ASICREV_IS(r, SPOOKY)
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#define ASICREV_IS_KALINDI(r) ASICREV_IS(r, KALINDI)
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#define ASICREV_IS_KALINDI_GODAVARI(r) ASICREV_IS(r, GODAVARI)
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#define ASICREV_IS_ICELAND_M(r) ASICREV_IS(r, ICELAND)
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#define ASICREV_IS_TONGA_P(r) ASICREV_IS(r, TONGA)
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#define ASICREV_IS_FIJI_P(r) ASICREV_IS(r, FIJI)
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#define ASICREV_IS_POLARIS10_P(r) ASICREV_IS(r, POLARIS10)
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#define ASICREV_IS_POLARIS11_M(r) ASICREV_IS(r, POLARIS11)
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#define ASICREV_IS_POLARIS12_V(r) ASICREV_IS(r, POLARIS12)
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#define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
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#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
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#define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
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#define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
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#define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
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#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
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#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
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#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
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#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
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#define ASICREV_IS_ALDEBARAN(r) ASICREV_IS(r, ALDEBARAN)
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#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
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#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
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#define ASICREV_IS_RENOIR(r) ASICREV_IS(r, RENOIR)
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#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
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#define ASICREV_IS_NAVI12_P(r) ASICREV_IS(r, NAVI12)
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#define ASICREV_IS_NAVI14_M(r) ASICREV_IS(r, NAVI14)
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#define ASICREV_IS_NAVI21_M(r) ASICREV_IS(r, NAVI21)
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#define ASICREV_IS_NAVI22_P(r) ASICREV_IS(r, NAVI22)
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#define ASICREV_IS_NAVI23_P(r) ASICREV_IS(r, NAVI23)
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#define ASICREV_IS_NAVI24_P(r) ASICREV_IS(r, NAVI24)
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#define ASICREV_IS_VANGOGH(r) ASICREV_IS(r, VANGOGH)
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#define ASICREV_IS_GFX1100(r) ASICREV_IS(r, GFX1100)
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#define ASICREV_IS_GFX1101(r) ASICREV_IS(r, GFX1101)
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#define ASICREV_IS_GFX1102(r) ASICREV_IS(r, GFX1102)
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#define ASICREV_IS_GFX1103(r) ASICREV_IS(r, GFX1103)
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#define ASICREV_IS_REMBRANDT(r) ASICREV_IS(r, REMBRANDT)
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#define ASICREV_IS_GFX1036(r) ASICREV_IS(r, GFX1036)
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#define ASICREV_IS_GFX1037(r) ASICREV_IS(r, GFX1037)
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#endif // _AMDGPU_ASIC_ADDR_H
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