rocm-systems/tests/workloads/vcopy/MI100/pmc_perf_15.csv

1	Dispatch_ID	Kernel_Name	GPU_ID	queue-id	queue-index	pid	tid	Grid_Size	Workgroup_Size	LDS_Per_Workgroup	Scratch_Per_Workitem	Arch_VGPR	Accum_VGPR	SGPR	wave_size	sig	obj	TCC_HIT[0]	TCC_MISS[0]	TCC_READ[0]	TCC_REQ[0]	TCC_HIT[1]	TCC_MISS[1]	TCC_READ[1]	TCC_REQ[1]	TCC_HIT[2]	TCC_MISS[2]	TCC_READ[2]	TCC_REQ[2]	TCC_HIT[3]	TCC_MISS[3]	TCC_READ[3]	TCC_REQ[3]	TCC_HIT[4]	TCC_MISS[4]	TCC_READ[4]	TCC_REQ[4]	TCC_HIT[5]	TCC_MISS[5]	TCC_READ[5]	TCC_REQ[5]	TCC_HIT[6]	TCC_MISS[6]	TCC_READ[6]	TCC_REQ[6]	TCC_HIT[7]	TCC_MISS[7]	TCC_READ[7]	TCC_REQ[7]	TCC_HIT[8]	TCC_MISS[8]	TCC_READ[8]	TCC_REQ[8]	TCC_HIT[9]	TCC_MISS[9]	TCC_READ[9]	TCC_REQ[9]	TCC_HIT[10]	TCC_MISS[10]	TCC_READ[10]	TCC_REQ[10]	TCC_HIT[11]	TCC_MISS[11]	TCC_READ[11]	TCC_REQ[11]	TCC_HIT[12]	TCC_MISS[12]	TCC_READ[12]	TCC_REQ[12]	TCC_HIT[13]	TCC_MISS[13]	TCC_READ[13]	TCC_REQ[13]	TCC_HIT[14]	TCC_MISS[14]	TCC_READ[14]	TCC_REQ[14]	TCC_HIT[15]	TCC_MISS[15]	TCC_READ[15]	TCC_REQ[15]	TCC_HIT[16]	TCC_MISS[16]	TCC_READ[16]	TCC_REQ[16]	TCC_HIT[17]	TCC_MISS[17]	TCC_READ[17]	TCC_REQ[17]	TCC_HIT[18]	TCC_MISS[18]	TCC_READ[18]	TCC_REQ[18]	TCC_HIT[19]	TCC_MISS[19]	TCC_READ[19]	TCC_REQ[19]	TCC_HIT[20]	TCC_MISS[20]	TCC_READ[20]	TCC_REQ[20]	TCC_HIT[21]	TCC_MISS[21]	TCC_READ[21]	TCC_REQ[21]	TCC_HIT[22]	TCC_MISS[22]	TCC_READ[22]	TCC_REQ[22]	TCC_HIT[23]	TCC_MISS[23]	TCC_READ[23]	TCC_REQ[23]	TCC_HIT[24]	TCC_MISS[24]	TCC_READ[24]	TCC_REQ[24]	TCC_HIT[25]	TCC_MISS[25]	TCC_READ[25]	TCC_REQ[25]	TCC_HIT[26]	TCC_MISS[26]	TCC_READ[26]	TCC_REQ[26]	TCC_HIT[27]	TCC_MISS[27]	TCC_READ[27]	TCC_REQ[27]	TCC_HIT[28]	TCC_MISS[28]	TCC_READ[28]	TCC_REQ[28]	TCC_HIT[29]	TCC_MISS[29]	TCC_READ[29]	TCC_REQ[29]	TCC_HIT[30]	TCC_MISS[30]	TCC_READ[30]	TCC_REQ[30]	TCC_HIT[31]	TCC_MISS[31]	TCC_READ[31]	TCC_REQ[31]	DispatchNs	Start_Timestamp	End_Timestamp	CompleteNs
2	0	vecCopy(double*, double*, double*, int, int)	2	0	0	2503605	2503605	1048576	256	0	0	8	8	16	64	0x0	0x7fb0a8d5ce80	47	8193	4144	8240	0	8430	4334	8430	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	141	8195	4240	8336	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8240	4144	8240	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8208	4112	8208	0	8192	4096	8192	0	8192	4096	8192	0	8240	4144	8240	0	8192	4096	8192	5255474735075905	5255477523602709	5255477523626869	5255474742830210
3	1	vecCopy(double*, double*, double*, int, int)	2	0	2	2503605	2503605	1048576	256	0	0	8	8	16	64	0x0	0x7fb0a8d5ce80	47	8193	4144	8240	0	8432	4336	8432	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8193	4097	8193	0	8195	4099	8195	0	8192	4096	8192	0	8192	4096	8192	0	8193	4097	8193	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8241	4145	8241	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8238	4142	8238	0	8192	4096	8192	0	8192	4096	8192	0	8240	4144	8240	0	8192	4096	8192	5255474742899311	5255477523727189	5255477523745909	5255474743409356
4	2	vecCopy(double*, double*, double*, int, int)	2	0	4	2503605	2503605	1048576	256	0	0	8	8	16	64	0x0	0x7fb0a8d5ce80	47	8193	4144	8240	0	8432	4336	8432	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8193	4097	8193	0	8195	4099	8195	0	8192	4096	8192	0	8192	4096	8192	0	8193	4097	8193	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8241	4145	8241	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8242	4146	8242	0	8192	4096	8192	0	8192	4096	8192	0	8240	4144	8240	0	8192	4096	8192	5255474743486331	5255477523767029	5255477523785909	5255474743827256