rocm-systems/tests/workloads/vcopy/MI100/pmc_perf_16.csv

1	Dispatch_ID	Kernel_Name	GPU_ID	queue-id	queue-index	pid	tid	Grid_Size	Workgroup_Size	LDS_Per_Workgroup	Scratch_Per_Workitem	Arch_VGPR	Accum_VGPR	SGPR	wave_size	sig	obj	TCC_RW_REQ[0]	TCC_TOO_MANY_EA_WRREQS_STALL[0]	TCC_WRITE[0]	TCC_RW_REQ[1]	TCC_TOO_MANY_EA_WRREQS_STALL[1]	TCC_WRITE[1]	TCC_RW_REQ[2]	TCC_TOO_MANY_EA_WRREQS_STALL[2]	TCC_WRITE[2]	TCC_RW_REQ[3]	TCC_TOO_MANY_EA_WRREQS_STALL[3]	TCC_WRITE[3]	TCC_RW_REQ[4]	TCC_TOO_MANY_EA_WRREQS_STALL[4]	TCC_WRITE[4]	TCC_RW_REQ[5]	TCC_TOO_MANY_EA_WRREQS_STALL[5]	TCC_WRITE[5]	TCC_RW_REQ[6]	TCC_TOO_MANY_EA_WRREQS_STALL[6]	TCC_WRITE[6]	TCC_RW_REQ[7]	TCC_TOO_MANY_EA_WRREQS_STALL[7]	TCC_WRITE[7]	TCC_RW_REQ[8]	TCC_TOO_MANY_EA_WRREQS_STALL[8]	TCC_WRITE[8]	TCC_RW_REQ[9]	TCC_TOO_MANY_EA_WRREQS_STALL[9]	TCC_WRITE[9]	TCC_RW_REQ[10]	TCC_TOO_MANY_EA_WRREQS_STALL[10]	TCC_WRITE[10]	TCC_RW_REQ[11]	TCC_TOO_MANY_EA_WRREQS_STALL[11]	TCC_WRITE[11]	TCC_RW_REQ[12]	TCC_TOO_MANY_EA_WRREQS_STALL[12]	TCC_WRITE[12]	TCC_RW_REQ[13]	TCC_TOO_MANY_EA_WRREQS_STALL[13]	TCC_WRITE[13]	TCC_RW_REQ[14]	TCC_TOO_MANY_EA_WRREQS_STALL[14]	TCC_WRITE[14]	TCC_RW_REQ[15]	TCC_TOO_MANY_EA_WRREQS_STALL[15]	TCC_WRITE[15]	TCC_RW_REQ[16]	TCC_TOO_MANY_EA_WRREQS_STALL[16]	TCC_WRITE[16]	TCC_RW_REQ[17]	TCC_TOO_MANY_EA_WRREQS_STALL[17]	TCC_WRITE[17]	TCC_RW_REQ[18]	TCC_TOO_MANY_EA_WRREQS_STALL[18]	TCC_WRITE[18]	TCC_RW_REQ[19]	TCC_TOO_MANY_EA_WRREQS_STALL[19]	TCC_WRITE[19]	TCC_RW_REQ[20]	TCC_TOO_MANY_EA_WRREQS_STALL[20]	TCC_WRITE[20]	TCC_RW_REQ[21]	TCC_TOO_MANY_EA_WRREQS_STALL[21]	TCC_WRITE[21]	TCC_RW_REQ[22]	TCC_TOO_MANY_EA_WRREQS_STALL[22]	TCC_WRITE[22]	TCC_RW_REQ[23]	TCC_TOO_MANY_EA_WRREQS_STALL[23]	TCC_WRITE[23]	TCC_RW_REQ[24]	TCC_TOO_MANY_EA_WRREQS_STALL[24]	TCC_WRITE[24]	TCC_RW_REQ[25]	TCC_TOO_MANY_EA_WRREQS_STALL[25]	TCC_WRITE[25]	TCC_RW_REQ[26]	TCC_TOO_MANY_EA_WRREQS_STALL[26]	TCC_WRITE[26]	TCC_RW_REQ[27]	TCC_TOO_MANY_EA_WRREQS_STALL[27]	TCC_WRITE[27]	TCC_RW_REQ[28]	TCC_TOO_MANY_EA_WRREQS_STALL[28]	TCC_WRITE[28]	TCC_RW_REQ[29]	TCC_TOO_MANY_EA_WRREQS_STALL[29]	TCC_WRITE[29]	TCC_RW_REQ[30]	TCC_TOO_MANY_EA_WRREQS_STALL[30]	TCC_WRITE[30]	TCC_RW_REQ[31]	TCC_TOO_MANY_EA_WRREQS_STALL[31]	TCC_WRITE[31]	DispatchNs	Start_Timestamp	End_Timestamp	CompleteNs
2	0	vecCopy(double*, double*, double*, int, int)	2	0	0	2504007	2504007	1048576	256	0	0	8	8	16	64	0x0	0x7f57fe5e8e80	8192	0	4096	8192	0	4096	8336	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	5255476648728339	5255477523602709	5255477523626869	5255476656514154
3	1	vecCopy(double*, double*, double*, int, int)	2	0	2	2504007	2504007	1048576	256	0	0	8	8	16	64	0x0	0x7f57fe5e8e80	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	5255476656566463	5255477523727189	5255477523745909	5255476657042643
4	2	vecCopy(double*, double*, double*, int, int)	2	0	4	2504007	2504007	1048576	256	0	0	8	8	16	64	0x0	0x7f57fe5e8e80	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	5255476657106815	5255477523767029	5255477523785909	5255476657435246