Shweta.Khatri
6f6f02f352
Intentionally trigger sw exceptions to verify GPU can handle abnormal scenarios Change-Id: Ie80aa21883a912834ce6d917ecbb21ff6b3145f5 Signed-off-by: Chris Freehill <cfreehil@amd.com>
77 lines
3.1 KiB
Common Lisp
77 lines
3.1 KiB
Common Lisp
/*
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* =============================================================================
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* ROC Runtime Conformance Release License
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* =============================================================================
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* The University of Illinois/NCSA
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* Open Source License (NCSA)
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*
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* Copyright (c) 2024, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Developed by:
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*
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* AMD Research and AMD ROC Software Development
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*
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* Advanced Micro Devices, Inc.
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*
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* www.amd.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal with the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimers.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimers in
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* the documentation and/or other materials provided with the distribution.
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* - Neither the names of <Name of Development Group, Name of Institution>,
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* nor the names of its contributors may be used to endorse or promote
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* products derived from this Software without specific prior written
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* permission.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS WITH THE SOFTWARE.
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*
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*/
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__kernel void trigger_s_trap(__global int* dstArray, __global const int* srcArray, const int sz) {
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// Obtain the unique ID of the work-item
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size_t id = get_global_id(0);
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// Adding this line _just_ to avoid any compiler optimization of this kernel
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dstArray[id] = srcArray[id] * srcArray[id];
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// Explicitly trigger a software trap on the first thread using AMDGCN assembly
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if (id == 0) {
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__asm__ volatile("s_trap 1");
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}
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}
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__kernel void trigger_memory_violation(__global int* dstArray, __global const int* srcArray,
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const int sz) {
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// Obtain the unique ID of the work-item
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size_t id = get_global_id(0);
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// Adding this line _just_ to avoid any compiler optimization of this kernel
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dstArray[id] = srcArray[id] * srcArray[id];
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if (id == 0) {
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// Point to a garbage memory location
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int* invalidPtr = (int*)0xdeadbeef;
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// Try to read from and also write to the garbage memory location to trigger a memory violation
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int invalidData = *invalidPtr;
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*invalidPtr = 42;
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}
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}
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