Files
rocm-systems/tests/workloads/ipblocks_SQ_SPI/MI100/pmc_perf.csv
T
JoseSantosAMD da506ad9b5 Pytest add mi200 to analyze workloads (#334)
* Updated links in documentation. (#328)

Updated to reflect new GitHub organization.
Fixed broken links to GitHub pages.

Signed-off-by: David Galiffi <David.Galiffi@amd.com>

* update branch for 2.x documentation builds

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* update checkout action and use concurrency instead of cancel-workflow-action

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* test addition of user option for container launch

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* remove --user option for container, try chown instead

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* fixing yaml syntax

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* reorder job step - start with checkout

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* restore missing run directive

Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>

* Update workloads to include log.txt
Add missing MI200 workloads

Signed-off-by: Jose Santos <josantos@amd.com>

* Signed-off-by: Jose Santos <josantos@amd.com>
Add vcopy workload for tests

* Change exit codes for caught failures

Signed-off-by: Jose Santos <josantos@amd.com>

* reformat

Signed-off-by: Jose Santos <josantos@amd.com>

* Add pytest-xdist for pytest -n

Signed-off-by: Jose Santos <josantos@amd.com>

---------

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
Signed-off-by: Jose Santos <josantos@amd.com>
Co-authored-by: David Galiffi <David.Galiffi@amd.com>
Co-authored-by: Karl W. Schulz <karl.schulz@amd.com>
2024-04-01 14:30:21 -05:00

4.0 KiB

1Dispatch_IDKernel_NameGPU_IDGrid_SizeWorkgroup_SizeLDS_Per_WorkgroupScratch_Per_WorkitemArch_VGPRAccum_VGPRSGPRwave_sizeobjSQ_WAVES_SAVEDSQ_INSTS_SMEM_NORMSQC_TC_INST_REQSQC_TC_DATA_READ_REQSQC_TC_DATA_WRITE_REQSQC_TC_DATA_ATOMIC_REQSQC_TC_STALLSQC_TC_REQSPI_RA_BAR_CU_FULL_CSNSPI_RA_TGLIM_CU_FULL_CSNwave_size_1obj_1SQ_INSTS_SMEMSQ_INSTS_FLATSQ_INSTS_LDSSQ_INSTS_GDSSQ_INSTS_EXP_GDSSQ_INSTS_BRANCHSQ_INSTS_SENDMSGSQ_INSTSGRBM_SPI_BUSYSPI_CSN_NUM_THREADGROUPSSPI_CSN_WAVEwave_size_2obj_2SQ_CYCLESSQ_BUSY_CYCLESSQ_WAVESSQ_INSTS_VMEM_WRSQ_INSTS_VMEM_RDSQ_INSTS_VMEMSQ_INSTS_SALUSQ_INSTS_VSKIPPEDGRBM_COUNTGRBM_GUI_ACTIVESPI_CSN_WINDOW_VALIDSPI_CSN_BUSYwave_size_3obj_3SQ_INST_CYCLES_SALUSQ_THREAD_CYCLES_VALUSQ_IFETCHSQ_LDS_BANK_CONFLICTSQ_LDS_ADDR_CONFLICTSQ_LDS_UNALIGNED_STALLSQ_WAVES_EQ_64SQ_WAVES_LT_64SPI_RA_WAVE_SIMD_FULL_CSNSPI_RA_VGPR_SIMD_FULL_CSNwave_size_4obj_4SQ_WAVE_CYCLESSQ_WAIT_ANYSQ_WAIT_INST_ANYSQ_ACTIVE_INST_ANYSQ_BUSY_CU_CYCLESSQ_INSTS_VALUSQ_ACTIVE_INST_VMEMSQ_ACTIVE_INST_LDSSPI_RA_REQ_NO_ALLOCSPI_RA_REQ_NO_ALLOC_CSNwave_size_5obj_5SQ_WAVES_LT_48SQ_WAVES_LT_32SQ_WAVES_LT_16SQ_ITEMSSQ_LDS_MEM_VIOLATIONSSQ_LDS_ATOMIC_RETURNSQ_LDS_IDX_ACTIVESQ_WAVES_RESTOREDSPI_RA_SGPR_SIMD_FULL_CSNSPI_RA_LDS_CU_FULL_CSNwave_size_6obj_6SQ_ACTIVE_INST_VALUSQ_ACTIVE_INST_SCASQ_ACTIVE_INST_EXP_GDSSQ_ACTIVE_INST_MISCSQ_ACTIVE_INST_FLATSQ_INST_CYCLES_VMEM_WRSQ_INST_CYCLES_VMEM_RDSQ_INST_CYCLES_SMEMSPI_RA_RES_STALL_CSNSPI_RA_TMP_STALL_CSNwave_size_7obj_7SQC_DCACHE_REQSQC_DCACHE_HITSSQC_DCACHE_MISSESSQC_DCACHE_MISSES_DUPLICATESQC_DCACHE_REQ_READ_1SQC_DCACHE_REQ_READ_2SQC_DCACHE_REQ_READ_4SPI_VWC_CSC_WRSPI_RA_BULKY_CU_FULL_CSNwave_size_8obj_8SQC_DCACHE_REQ_READ_16SQC_ICACHE_REQSQC_ICACHE_HITSSQC_ICACHE_MISSESSQC_ICACHE_MISSES_DUPLICATESQC_DCACHE_INPUT_VALID_READYBSQC_DCACHE_ATOMICSQC_DCACHE_REQ_READ_8SPI_RA_WVLIM_STALL_CSNSPI_SWC_CSC_WRStart_TimestampEnd_Timestamp
20vecCopy(double*, double*, double*, int, int) [clone .kd]21048576256008816640x7ff0c6e6cec001310721444800019200640x7f27479d0ec06553632768000163841638439321631956409616384640x7f0496b68ec0389544236775163841638416384327684915204869248692387831246710640x7f245a784ec049152115343366553600016384000640x7f3b2a660ec0250866242277180919543673604483448287163840001426030644640x7efcd2d2cec00001048576000000640x7f8092100ec01802241146880327683276816384163846553600640x7f04f6d1cec0655366404848144032768327680163840640x7ff14359cec0065536644534814721843510008192014100867595225221410086759546522
31vecCopy(double*, double*, double*, int, int) [clone .kd]21048576256008816640x7ff0c6e6cec001310720480004800640x7f27479d0ec06553632768000163841638439321630906409616384640x7f0496b68ec0348232234401163841638416384327684915204352843528348224244193640x7f245a784ec049152115343366553600016384000640x7f3b2a660ec0246474702305711512299073604483368535163840001420730591640x7efcd2d2cec00001048576000000640x7f8092100ec01802241146880327683276816384163846553600640x7f04f6d1cec0655366404848144032768327680163840640x7ff14359cec006553665536001919290008192014100867596490821410086759668282
42vecCopy(double*, double*, double*, int, int) [clone .kd]21048576256008816640x7ff0c6e6cec001310720480004800640x7f27479d0ec06553632768000163841638439321630772409616384640x7f0496b68ec0345416234002163841638416384327684915204317643176345408243779640x7f245a784ec049152115343366553600016384000640x7f3b2a660ec0240850162250443312201353604483343834163840001253228916640x7efcd2d2cec00001048576000000640x7f8092100ec01802241146880327683276816384163846553600640x7f04f6d1cec0655366404848144032768327680163840640x7ff14359cec006553665536001867990008192014100867596871621410086759706362