JoseSantosAMD
da506ad9b5
* Updated links in documentation. (#328) Updated to reflect new GitHub organization. Fixed broken links to GitHub pages. Signed-off-by: David Galiffi <David.Galiffi@amd.com> * update branch for 2.x documentation builds Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * update checkout action and use concurrency instead of cancel-workflow-action Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * test addition of user option for container launch Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * remove --user option for container, try chown instead Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * fixing yaml syntax Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * reorder job step - start with checkout Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * restore missing run directive Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> * Update workloads to include log.txt Add missing MI200 workloads Signed-off-by: Jose Santos <josantos@amd.com> * Signed-off-by: Jose Santos <josantos@amd.com> Add vcopy workload for tests * Change exit codes for caught failures Signed-off-by: Jose Santos <josantos@amd.com> * reformat Signed-off-by: Jose Santos <josantos@amd.com> * Add pytest-xdist for pytest -n Signed-off-by: Jose Santos <josantos@amd.com> --------- Signed-off-by: David Galiffi <David.Galiffi@amd.com> Signed-off-by: Karl W. Schulz <karl.schulz@amd.com> Signed-off-by: Jose Santos <josantos@amd.com> Co-authored-by: David Galiffi <David.Galiffi@amd.com> Co-authored-by: Karl W. Schulz <karl.schulz@amd.com>
3.3 KiB
3.3 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | wave_size_1 | obj_1 | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | wave_size_2 | obj_2 | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | wave_size_3 | obj_3 | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | wave_size_4 | obj_4 | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | wave_size_5 | obj_5 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | wave_size_6 | obj_6 | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | wave_size_7 | obj_7 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_BUSY_CU_CYCLES | SQ_WAVES | SQ_WAVE_CYCLES | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | wave_size_8 | obj_8 | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | wave_size_9 | obj_9 | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f082dde8ec0 | 0.0 | 0.0 | 120.0 | 524288.0 | 64 | 0x7f4ce7cd0ec0 | 62569420.0 | 177352872.0 | 73126606.0 | 131072.0 | 64 | 0x7f5659524ec0 | 131072.0 | 131072.0 | 0.0 | 2431295.0 | 64 | 0x7fbf6dbe8ec0 | 0.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7ff977d08ec0 | 131072.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f34cb3d8ec0 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 64 | 0x7fd37d108ec0 | 0.0 | 0.0 | 0.0 | 32768.0 | 64 | 0x7fbc662a8ec0 | 388736 | 239917 | 3521723 | 16384 | 25498315 | 48591 | 48591 | 3951146.0 | 3076897.0 | 5152.0 | 1019652.0 | 64 | 0x7fb2b4a1cec0 | 0.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f0f78644ec0 | 960.0 | 513975.0 | 0.0 | 524288.0 | 1409999465186232 | 1409999465211512 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f082dde8ec0 | 0.0 | 0.0 | 120.0 | 524288.0 | 64 | 0x7f4ce7cd0ec0 | 62520313.0 | 168628497.0 | 68665656.0 | 131072.0 | 64 | 0x7f5659524ec0 | 131072.0 | 131072.0 | 0.0 | 2569317.0 | 64 | 0x7fbf6dbe8ec0 | 0.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7ff977d08ec0 | 131072.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f34cb3d8ec0 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 64 | 0x7fd37d108ec0 | 0.0 | 0.0 | 0.0 | 32768.0 | 64 | 0x7fbc662a8ec0 | 393368 | 227504 | 3203308 | 16384 | 22758957 | 49170 | 49170 | 3702176.0 | 3054979.0 | 5741.0 | 1069753.0 | 64 | 0x7fb2b4a1cec0 | 0.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f0f78644ec0 | 960.0 | 513986.0 | 0.0 | 524288.0 | 1409999465380472 | 1409999465399672 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f082dde8ec0 | 0.0 | 0.0 | 120.0 | 524288.0 | 64 | 0x7f4ce7cd0ec0 | 59852047.0 | 167341765.0 | 67534746.0 | 131072.0 | 64 | 0x7f5659524ec0 | 131072.0 | 131072.0 | 0.0 | 2500254.0 | 64 | 0x7fbf6dbe8ec0 | 0.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7ff977d08ec0 | 131072.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f34cb3d8ec0 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 64 | 0x7fd37d108ec0 | 0.0 | 0.0 | 0.0 | 32768.0 | 64 | 0x7fbc662a8ec0 | 340992 | 235913 | 3414629 | 16384 | 24427512 | 42623 | 42623 | 3836411.0 | 3115077.0 | 5181.0 | 1254701.0 | 64 | 0x7fb2b4a1cec0 | 0.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f0f78644ec0 | 960.0 | 513898.0 | 0.0 | 524288.0 | 1409999465420152 | 1409999465439192 |