vedithal-amd
f9aa7be97c
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
1.5 KiB
1.5 KiB
| 1 | Dispatch_ID | GPU_ID | Queue_ID | PID | TID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Start_Timestamp | End_Timestamp | Correlation_ID | Kernel_ID | CPC_CPC_UTCL2IU_IDLE | CPC_UTCL1_STALL_ON_TRANSLATION | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_RES_STALL_CSN | SQC_DCACHE_MISSES_DUPLICATE | SQ_INSTS_SMEM | SQ_INSTS_VALU_FMA_F32 | SQ_INSTS_VALU_INT32 | SQ_INSTS_VALU_MFMA_F8 | SQ_INSTS_VALU_MFMA_MOPS_F8 | SQ_INSTS_VALU_TRANS_F32 | SQ_THREAD_CYCLES_VALU | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | TCC_BUSY_sum | TCC_HIT_sum | TCC_NORMAL_WRITEBACK_sum | TCC_READ_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TCC_CC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_WRITE_REQ_sum |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1 | 15786 | 15786 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248228340675080 | 1248228340696799 | 1 | 13 | 76981.0 | 399.0 | 0.0 | 9346.0 | 2160.0 | 65536.0 | 0.0 | 49152.0 | 0.0 | 0.0 | 0.0 | 6291456.0 | 0.0 | 32768.0 | 533130.0 | 66864.0 | 30395.0 | 66936.0 | 0.0 | 0.0 | 0.0 | 131072.0 |
| 3 | 1 | 0 | 1 | 15786 | 15786 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248228341369934 | 1248228341386613 | 2 | 13 | 65633.0 | 0.0 | 0.0 | 3274.0 | 2160.0 | 65536.0 | 0.0 | 49152.0 | 0.0 | 0.0 | 0.0 | 6291456.0 | 0.0 | 32768.0 | 459164.0 | 66864.0 | 29343.0 | 66912.0 | 0.0 | 0.0 | 0.0 | 131072.0 |
| 4 | 2 | 0 | 1 | 15786 | 15786 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248228341957512 | 1248228341974431 | 3 | 13 | 62962.0 | 0.0 | 0.0 | 3253.0 | 2160.0 | 65536.0 | 0.0 | 49152.0 | 0.0 | 0.0 | 0.0 | 6291456.0 | 0.0 | 32768.0 | 460697.0 | 66864.0 | 29330.0 | 66904.0 | 0.0 | 0.0 | 0.0 | 131072.0 |