vedithal-amd
f9aa7be97c
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
1.1 KiB
1.1 KiB
| 1 | Dispatch_ID | GPU_ID | Queue_ID | PID | TID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Start_Timestamp | End_Timestamp | Correlation_ID | Kernel_ID | SPI_RA_LDS_CU_FULL_CSN | SPI_RA_TMP_STALL_CSN | SQC_DCACHE_REQ_READ_1 | SQC_ICACHE_HITS | SQ_INSTS_LDS_ATOMIC_BANDWIDTH | SQ_INSTS_MFMA | SQ_INSTS_VALU_MFMA_F6F4 | SQ_INSTS_VALU_MUL_F32 | SQ_LDS_ADDR_CONFLICT | SQ_WAIT_INST_ANY | TCC_EA0_RDREQ_32B_sum | TCC_EA0_RDREQ_sum | TCC_STREAMING_REQ_sum | TCC_WRITE_sum |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1 | 15807 | 15807 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248229989191714 | 1248229989213393 | 1 | 13 | 0.0 | 0.0 | 32768.0 | 64005.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 656853.0 | 0.0 | 65640.0 | 0.0 | 131072.0 |
| 3 | 1 | 0 | 1 | 15807 | 15807 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248229989539141 | 1248229989555860 | 2 | 13 | 0.0 | 0.0 | 32768.0 | 64262.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 95857.0 | 0.0 | 65612.0 | 0.0 | 131072.0 |
| 4 | 2 | 0 | 1 | 15807 | 15807 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248229989799091 | 1248229989816011 | 3 | 13 | 0.0 | 0.0 | 32768.0 | 64364.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 120606.0 | 0.0 | 65612.0 | 0.0 | 131072.0 |