Ioannis Assiouras
286 行
9.3 KiB
C++
286 行
9.3 KiB
C++
/* Copyright (c) 2010 - 2021 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#ifndef WITHOUT_HSA_BACKEND
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#include "top.hpp"
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#include "os/os.hpp"
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#include "device/device.hpp"
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#include "rocsettings.hpp"
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#include "device/rocm/rocglinterop.hpp"
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namespace roc {
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// ================================================================================================
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Settings::Settings() {
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// Initialize the HSA device default settings
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// Set this to true when we drop the flag
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doublePrecision_ = ::CL_KHR_FP64;
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enableLocalMemory_ = HSA_LOCAL_MEMORY_ENABLE;
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maxWorkGroupSize_ = 1024;
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preferredWorkGroupSize_ = 256;
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kernargPoolSize_ = HSA_KERNARG_POOL_SIZE;
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// Determine if user is requesting Non-Coherent mode
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// for system memory. By default system memory is
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// operates or is programmed to be in Coherent mode.
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// Users can turn it off for hardware that does not
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// support this feature naturally
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char* nonCoherentMode = getenv("OPENCL_USE_NC_MEMORY_POLICY");
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enableNCMode_ = (nonCoherentMode) ? true : false;
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// Disable image DMA by default (ROCM runtime doesn't support it)
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imageDMA_ = false;
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stagedXferRead_ = true;
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stagedXferWrite_ = true;
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stagedXferSize_ = flagIsDefault(GPU_STAGING_BUFFER_SIZE)
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? 1 * Mi : GPU_STAGING_BUFFER_SIZE * Mi;
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// Initialize transfer buffer size to 1MB by default
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xferBufSize_ = 1024 * Ki;
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pinnedXferSize_ = GPU_PINNED_MIN_XFER_SIZE * Mi;
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pinnedMinXferSize_ = flagIsDefault(GPU_PINNED_MIN_XFER_SIZE)
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? 1 * Mi : GPU_PINNED_MIN_XFER_SIZE * Mi;
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sdmaCopyThreshold_ = GPU_FORCE_BLIT_COPY_SIZE * Ki;
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// Don't support Denormals for single precision by default
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singleFpDenorm_ = false;
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apuSystem_ = false;
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// Device enqueuing settings
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numDeviceEvents_ = 1024;
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numWaitEvents_ = 8;
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useLightning_ = (!flagIsDefault(GPU_ENABLE_LC)) ? GPU_ENABLE_LC : true;
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lcWavefrontSize64_ = true;
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imageBufferWar_ = false;
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sdma_p2p_threshold_ = ROC_P2P_SDMA_SIZE * Ki;
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hmmFlags_ = (!flagIsDefault(ROC_HMM_FLAGS)) ? ROC_HMM_FLAGS : 0;
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rocr_backend_ = true;
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cpu_wait_for_signal_ = !AMD_DIRECT_DISPATCH;
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cpu_wait_for_signal_ = (!flagIsDefault(ROC_CPU_WAIT_FOR_SIGNAL)) ?
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ROC_CPU_WAIT_FOR_SIGNAL : cpu_wait_for_signal_;
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system_scope_signal_ = ROC_SYSTEM_SCOPE_SIGNAL;
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// Use coarse grain system memory for kernel arguments by default (to keep GPU cache)
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fgs_kernel_arg_ = false;
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barrier_value_packet_ = false;
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kernel_arg_impl_ = KernelArgImpl::HostKernelArgs;
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gwsInitSupported_ = true;
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limit_blit_wg_ = 16;
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}
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// ================================================================================================
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bool Settings::create(bool fullProfile, const amd::Isa& isa,
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bool enableXNACK, bool coop_groups,
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bool isXgmi, bool hasValidHDPFlush) {
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uint32_t gfxipMajor = isa.versionMajor();
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uint32_t gfxipMinor = isa.versionMinor();
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uint32_t gfxStepping = isa.versionStepping();
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customHostAllocator_ = false;
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if (fullProfile) {
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pinnedXferSize_ = 0;
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stagedXferSize_ = 0;
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xferBufSize_ = 0;
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apuSystem_ = true;
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} else {
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pinnedXferSize_ = std::max(pinnedXferSize_, pinnedMinXferSize_);
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stagedXferSize_ = std::max(stagedXferSize_, pinnedMinXferSize_ + 4 * Ki);
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}
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enableXNACK_ = enableXNACK;
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hsailExplicitXnack_ = enableXNACK;
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// Enable extensions
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enableExtension(ClKhrByteAddressableStore);
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enableExtension(ClKhrGlobalInt32BaseAtomics);
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enableExtension(ClKhrGlobalInt32ExtendedAtomics);
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enableExtension(ClKhrLocalInt32BaseAtomics);
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enableExtension(ClKhrLocalInt32ExtendedAtomics);
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enableExtension(ClKhrInt64BaseAtomics);
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enableExtension(ClKhrInt64ExtendedAtomics);
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enableExtension(ClKhr3DImageWrites);
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enableExtension(ClAmdMediaOps);
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enableExtension(ClAmdMediaOps2);
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enableExtension(ClKhrImage2dFromBuffer);
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if (MesaInterop::Supported()) {
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enableExtension(ClKhrGlSharing);
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}
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// Enable platform extension
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enableExtension(ClAmdDeviceAttributeQuery);
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// Enable KHR double precision extension
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enableExtension(ClKhrFp64);
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enableExtension(ClKhrSubGroups);
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enableExtension(ClKhrDepthImages);
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enableExtension(ClAmdCopyBufferP2P);
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enableExtension(ClKhrFp16);
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supportDepthsRGB_ = true;
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if (useLightning_) {
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enableExtension(ClAmdAssemblyProgram);
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// enable subnormals for gfx900 and later
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if (gfxipMajor >= 9) {
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singleFpDenorm_ = true;
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enableCoopGroups_ = GPU_ENABLE_COOP_GROUPS & coop_groups;
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enableCoopMultiDeviceGroups_ = GPU_ENABLE_COOP_GROUPS & coop_groups;
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}
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} else {
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// Also enable AMD double precision extension?
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enableExtension(ClAmdFp64);
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}
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if ((gfxipMajor == 9 && gfxipMinor == 0 && gfxStepping == 10) ||
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((gfxipMajor == 9 && gfxipMinor == 4 &&
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(gfxStepping == 0 || gfxStepping == 1 || gfxStepping == 2)))) {
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// Enable Barrier Value packet is only for MI2XX/300
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barrier_value_packet_ = true;
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}
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setKernelArgImpl(isa, isXgmi, hasValidHDPFlush);
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if (gfxipMajor >= 10) {
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enableWave32Mode_ = true;
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enableWgpMode_ = GPU_ENABLE_WGP_MODE;
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if (gfxipMinor == 1) {
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// GFX10.1 HW doesn't support custom pitch. Enable double copy workaround
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// TODO: This should be updated when ROCr support custom pitch
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imageBufferWar_ = GPU_IMAGE_BUFFER_WAR;
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}
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}
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if (!flagIsDefault(GPU_ENABLE_WAVE32_MODE)) {
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enableWave32Mode_ = GPU_ENABLE_WAVE32_MODE;
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}
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lcWavefrontSize64_ = !enableWave32Mode_;
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if (gfxipMajor > 10 || (gfxipMajor == 9 && gfxipMinor == 4)) {
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gwsInitSupported_ = false;
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}
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// Override current device settings
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override();
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return true;
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}
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// ================================================================================================
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void Settings::override() {
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// Limit reported workgroup size
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if (GPU_MAX_WORKGROUP_SIZE != 0) {
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preferredWorkGroupSize_ = GPU_MAX_WORKGROUP_SIZE;
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}
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if (!flagIsDefault(GPU_XFER_BUFFER_SIZE)) {
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xferBufSize_ = GPU_XFER_BUFFER_SIZE * Ki;
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}
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if (!flagIsDefault(GPU_PINNED_MIN_XFER_SIZE)) {
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pinnedMinXferSize_ = std::min(GPU_PINNED_MIN_XFER_SIZE * Ki, pinnedXferSize_);
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}
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if (!flagIsDefault(AMD_GPU_FORCE_SINGLE_FP_DENORM)) {
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switch (AMD_GPU_FORCE_SINGLE_FP_DENORM) {
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case 0:
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singleFpDenorm_ = false;
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break;
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case 1:
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singleFpDenorm_ = true;
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break;
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default:
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break;
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}
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}
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if (!flagIsDefault(GPU_ENABLE_COOP_GROUPS)) {
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enableCoopGroups_ = GPU_ENABLE_COOP_GROUPS;
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enableCoopMultiDeviceGroups_ = GPU_ENABLE_COOP_GROUPS;
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}
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if (!flagIsDefault(ROC_USE_FGS_KERNARG)) {
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fgs_kernel_arg_ = ROC_USE_FGS_KERNARG;
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}
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if (!flagIsDefault(DEBUG_CLR_BLIT_KERNARG_OPT)) {
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kernel_arg_opt_ = DEBUG_CLR_BLIT_KERNARG_OPT;
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}
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}
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// ================================================================================================
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void Settings::setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidHDPFlush) {
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const uint32_t gfxipMajor = isa.versionMajor();
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const uint32_t gfxipMinor = isa.versionMinor();
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const uint32_t gfxStepping = isa.versionStepping();
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const bool isMI300 = gfxipMajor == 9 && gfxipMinor == 4 &&
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(gfxStepping == 0 || gfxStepping == 1 || gfxStepping == 2);
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const bool isMI200 = (gfxipMajor == 9 && gfxipMinor == 0 && gfxStepping == 10);
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const bool isMI100 = (gfxipMajor == 9 && gfxipMinor == 0 && gfxStepping == 8);
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const bool isNavi = (gfxipMajor >= 10);
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auto kernelArgImpl = KernelArgImpl::HostKernelArgs;
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if (isXgmi) {
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// The XGMI-connected path does not require the manual memory ordering
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// workarounds that the PCIe connected path requires
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kernelArgImpl = KernelArgImpl::DeviceKernelArgs;
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} else if (isMI300 || isMI200) {
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// Implement the kernel argument readback workaround. It works only on
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// MI200, MI300 because of the strict guarantee on ordering of
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// stores in those ASICS
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kernelArgImpl = KernelArgImpl::DeviceKernelArgsReadback;
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} else if (hasValidHDPFlush && (isNavi || isMI100)) {
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// For dev >= gfx10 and MI100 ASICS implement the HDP flush to MMIO if the
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// HDP flush register is valid
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kernelArgImpl = KernelArgImpl::DeviceKernelArgsHDP;
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}
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// Enable device kernel args for MI300* for now
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if (isMI300) {
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kernel_arg_impl_ = kernelArgImpl;
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kernel_arg_opt_ = true;
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}
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if (!flagIsDefault(HIP_FORCE_DEV_KERNARG)) {
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kernel_arg_impl_ = kernelArgImpl & (HIP_FORCE_DEV_KERNARG ? 0xF : 0x0);
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}
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}
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} // namespace roc
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#endif // WITHOUT_HSA_BACKEND
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