colramos-amd
265c0f4856
Co-authored-by: Nick Curtis <nicholas.curtis@amd.com>
Signed-off-by: colramos-amd <colramos@amd.com>
[ROCm/rocprofiler-compute commit: 54f0fa8c81]
114 rader
3.5 KiB
Plaintext
114 rader
3.5 KiB
Plaintext
/*
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##############################################################################bl
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# MIT License
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#
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# Copyright (c) 2021 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in all
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# copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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##############################################################################el
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A instruction mix exerciser example, written by Gina Sitaraman and Nicholas Curtis [AMD].
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Although inline assembly is inherently unportable, this is expected to work on all CDNA accelerators.
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*/
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#include "common.h"
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__global__ void kernelasm() {
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// int32
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int i, j;
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asm volatile("v_add_u32_e32 %0, %1, %0\n" : "=v"(j) : "v"(i));
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// int 64
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long int l1, l2;
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asm volatile("v_cmp_eq_i64 %0, %1\n" : "=v"(l2) : "v"(l1), "v"(i));
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// fp32: add, mul, transcendental and fma
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float f1, f2;
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asm volatile(
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"v_add_f32_e32 %0, %1, %0\n"
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"v_mul_f32_e32 %0, %1, %0\n"
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"v_sqrt_f32 %0, %1\n"
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"v_fma_f32 %0, %1, %0, %1\n"
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: "=v"(f1)
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: "v"(f2));
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// fp64: add, mul, transcendental and fma
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double d1, d2, d3, d4;
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asm volatile(
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"v_add_f64 %0, %1, %0\n"
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"v_mul_f64 %0, %1, %0\n"
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"v_fma_f64 %0, %1, %0, %1\n"
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"v_sqrt_f64 %0, %1\n"
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"v_min_f64 %0, %1, %0\n"
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: "+v"(d1)
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: "v"(d2));
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// fp16: add, mul, transcendental and fma
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_Float16 h1, h2;
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asm volatile(
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"v_add_f16_e32 %0, %1, %0\n"
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"v_mul_f16_e32 %0, %1, %0\n"
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"v_sqrt_f16 %0, %1\n"
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"v_cvt_f16_f32 %0 %2\n"
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"v_fma_f16 %0, %1, %0, %0\n"
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: "=v"(h2)
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: "v"(h1), "v"(f1));
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// MFMA ops
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double2 dd;
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unsigned short us;
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long2 ll;
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#if defined(__gfx90a__)
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asm volatile("v_mfma_f64_4x4x4f64 %0 %1 %2 %3\n"
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: "=v"(d4)
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: "v"(d1), "v"(d2), "v"(d3));
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asm volatile("v_mfma_f32_16x16x4f32 %0 %1 %2 1\n"
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: "=v"(dd)
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: "v"(f1), "v"(f2));
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asm volatile("v_mfma_f32_16x16x16f16 %0 %1 %2 1\n"
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: "=v"(dd)
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: "v"(d1), "v"(d2));
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asm volatile("v_mfma_f32_16x16x8bf16 %0 %1 %2 1\n"
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: "=v"(dd)
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: "v"(f1), "v"(f2));
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asm volatile("v_mfma_i32_16x16x16i8 %0 %1 %2 1\n"
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: "=v"(ll)
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: "v"(i), "v"(j));
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#endif
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// Scalar op
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asm volatile("s_add_i32 %0 %1 %0\n" : "=s"(j) : "s"(i));
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// LDS
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asm volatile("ds_read_b32 %0 %0\n" : "=v"(i) : "v"(j));
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// Branch
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asm volatile(
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"s_branch .LDUMMY\n"
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".LDUMMY:\n"
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"s_endpgm\n");
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}
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int main() {
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kernelasm<<<1, 64>>>();
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hipCheck(hipDeviceSynchronize());
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}
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