Aditya Atluri
c286bf6f8a
1. Removed HIP_EXPERIMENTAL env variable so that device code will be accessed from LLVM IR 2. Removed soft support from headers and moved to hip_fp16.cpp 3. Added LLVM IR + inline asm to hip_ir.ll 4. Added test for fp16 5. Added barriers for hcc 3.5 and hcc 4.0 for half support a. Which means, hcc 4.0 can parse __fp16 but hcc 3.5 cant b. HCC 4.0 code is implemented now, hcc 3.5 will be added later Change-Id: Ic37859b2688ebb02e168bab643d1882bf4727952
67 γραμμές
1.9 KiB
LLVM
67 γραμμές
1.9 KiB
LLVM
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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target triple = "amdgcn--amdhsa"
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define linkonce_odr spir_func void @__threadfence() #1 {
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fence syncscope(2) seq_cst
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ret void
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}
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define linkonce_odr spir_func void @__threadfence_block() #1 {
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fence syncscope(3) seq_cst
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ret void
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}
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; Lightning does not support inline asm for 16-bit data types
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; So, bitcast half to short and then extend to 32bit i32
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; After inline asm, convert back to half
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define half @__hip_hc_ir_hadd_half(half %a, half %b) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = zext i16 %1 to i32
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%4 = zext i16 %2 to i32
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%5 = tail call i32 asm "v_add_f16 $0, $1, $2","=v,v,v"(i32 %3, i32 %4)
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%6 = trunc i32 %5 to i16
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%7 = bitcast i16 %6 to half
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ret half %7
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}
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define half @__hip_hc_ir_hsub_half(half %a, half %b) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = zext i16 %1 to i32
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%4 = zext i16 %2 to i32
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%5 = tail call i32 asm "v_sub_f16 $0, $1, $2","=v,v,v"(i32 %3, i32 %4)
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%6 = trunc i32 %5 to i16
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%7 = bitcast i16 %6 to half
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ret half %7
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}
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define half @__hip_hc_ir_hmul_half(half %a, half %b) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = zext i16 %1 to i32
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%4 = zext i16 %2 to i32
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%5 = tail call i32 asm "v_mul_f16 $0, $1, $2","=v,v,v"(i32 %3, i32 %4)
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%6 = trunc i32 %5 to i16
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%7 = bitcast i16 %6 to half
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ret half %7
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}
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define half @__hip_hc_ir_hfma_half(half %a, half %b, half %c) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = bitcast half %c to i16
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%4 = zext i16 %1 to i32
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%5 = zext i16 %2 to i32
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%6 = zext i16 %3 to i32
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%7 = tail call i32 asm "v_mad_f16 $0, $1, $2, $3","=v,v,v,v"(i32 %4, i32 %5, i32 %6)
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%8 = trunc i32 %7 to i16
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%9 = bitcast i16 %8 to half
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ret half %9
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}
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attributes #1 = { alwaysinline nounwind }
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