rocm-systems/tests/workloads/dispatch_2/MI200/pmc_perf.csv

1	Dispatch_ID	Kernel_Name	GPU_ID	Grid_Size	Workgroup_Size	LDS_Per_Workgroup	Scratch_Per_Workitem	Arch_VGPR	Accum_VGPR	SGPR	wave_size	obj	SQ_INSTS_VALU_MUL_F32	SQ_INSTS_VALU_FMA_F32	SQ_INSTS_VALU_TRANS_F32	SQ_INSTS_VALU_ADD_F64	SQ_INSTS_VALU_MUL_F64	SQ_INSTS_VALU_FMA_F64	SQ_INSTS_VALU_TRANS_F64	SQ_INSTS_VALU_INT32	TCP_VOLATILE_sum	TCP_TOTAL_ACCESSES_sum	TCP_TOTAL_READ_sum	TCP_TOTAL_WRITE_sum	TA_BUFFER_ATOMIC_WAVEFRONTS_sum	TA_BUFFER_TOTAL_CYCLES_sum	TD_ATOMIC_WAVEFRONT_sum	TD_STORE_WAVEFRONT_sum	SPI_RA_REQ_NO_ALLOC	SPI_RA_REQ_NO_ALLOC_CSN	CPC_CPC_STAT_STALL	CPC_UTCL1_STALL_ON_TRANSLATION	CPF_CPF_STAT_IDLE	CPF_CPF_TCIU_IDLE	TCC_REQ_sum	TCC_STREAMING_REQ_sum	TCC_HIT_sum	TCC_MISS_sum	wave_size_1	obj_1	SQ_WAVE_CYCLES	SQ_WAIT_ANY	SQ_WAIT_INST_ANY	SQ_ACTIVE_INST_ANY	SQ_BUSY_CU_CYCLES	SQ_ACTIVE_INST_VMEM	SQ_ACTIVE_INST_LDS	SQ_ACTIVE_INST_VALU	TCP_UTCL1_TRANSLATION_MISS_sum	TCP_UTCL1_TRANSLATION_HIT_sum	TCP_UTCL1_PERMISSION_MISS_sum	TCP_UTCL1_REQUEST_sum	TA_ADDR_STALLED_BY_TC_CYCLES_sum	TA_TOTAL_WAVEFRONTS_sum	SPI_RA_WAVE_SIMD_FULL_CSN	SPI_RA_VGPR_SIMD_FULL_CSN	CPC_CPC_UTCL2IU_STALL	CPC_ME1_BUSY_FOR_PACKET_DECODE	TCC_EA_WRREQ_sum	TCC_EA_WRREQ_64B_sum	TCC_EA_WR_UNCACHED_32B_sum	TCC_EA_WRREQ_DRAM_sum	wave_size_2	obj_2	SQ_WAVES_LT_32	SQ_WAVES_LT_16	SQ_ITEMS	SQ_LDS_MEM_VIOLATIONS	SQ_LDS_ATOMIC_RETURN	SQ_LDS_IDX_ACTIVE	SQ_WAVES_RESTORED	SQ_WAVES_SAVED	TCP_TCC_NC_WRITE_REQ_sum	TCP_TCC_NC_ATOMIC_REQ_sum	TCP_TCC_UC_READ_REQ_sum	TCP_TCC_UC_WRITE_REQ_sum	TA_FLAT_WRITE_WAVEFRONTS_sum	TA_FLAT_ATOMIC_WAVEFRONTS_sum	SPI_RA_WVLIM_STALL_CSN	SPI_SWC_CSC_WR	TCC_NORMAL_EVICT_sum	TCC_ALL_TC_OP_INV_EVICT_sum	TCC_TOO_MANY_EA_WRREQS_STALL_sum	TCC_EA_ATOMIC_sum	wave_size_3	obj_3	TCC_RW_REQ[0]	TCC_TOO_MANY_EA_WRREQS_STALL[0]	TCC_WRITE[0]	TCC_RW_REQ[1]	TCC_TOO_MANY_EA_WRREQS_STALL[1]	TCC_WRITE[1]	TCC_RW_REQ[2]	TCC_TOO_MANY_EA_WRREQS_STALL[2]	TCC_WRITE[2]	TCC_RW_REQ[3]	TCC_TOO_MANY_EA_WRREQS_STALL[3]	TCC_WRITE[3]	TCC_RW_REQ[4]	TCC_TOO_MANY_EA_WRREQS_STALL[4]	TCC_WRITE[4]	TCC_RW_REQ[5]	TCC_TOO_MANY_EA_WRREQS_STALL[5]	TCC_WRITE[5]	TCC_RW_REQ[6]	TCC_TOO_MANY_EA_WRREQS_STALL[6]	TCC_WRITE[6]	TCC_RW_REQ[7]	TCC_TOO_MANY_EA_WRREQS_STALL[7]	TCC_WRITE[7]	TCC_RW_REQ[8]	TCC_TOO_MANY_EA_WRREQS_STALL[8]	TCC_WRITE[8]	TCC_RW_REQ[9]	TCC_TOO_MANY_EA_WRREQS_STALL[9]	TCC_WRITE[9]	TCC_RW_REQ[10]	TCC_TOO_MANY_EA_WRREQS_STALL[10]	TCC_WRITE[10]	TCC_RW_REQ[11]	TCC_TOO_MANY_EA_WRREQS_STALL[11]	TCC_WRITE[11]	TCC_RW_REQ[12]	TCC_TOO_MANY_EA_WRREQS_STALL[12]	TCC_WRITE[12]	TCC_RW_REQ[13]	TCC_TOO_MANY_EA_WRREQS_STALL[13]	TCC_WRITE[13]	TCC_RW_REQ[14]	TCC_TOO_MANY_EA_WRREQS_STALL[14]	TCC_WRITE[14]	TCC_RW_REQ[15]	TCC_TOO_MANY_EA_WRREQS_STALL[15]	TCC_WRITE[15]	TCC_RW_REQ[16]	TCC_TOO_MANY_EA_WRREQS_STALL[16]	TCC_WRITE[16]	TCC_RW_REQ[17]	TCC_TOO_MANY_EA_WRREQS_STALL[17]	TCC_WRITE[17]	TCC_RW_REQ[18]	TCC_TOO_MANY_EA_WRREQS_STALL[18]	TCC_WRITE[18]	TCC_RW_REQ[19]	TCC_TOO_MANY_EA_WRREQS_STALL[19]	TCC_WRITE[19]	TCC_RW_REQ[20]	TCC_TOO_MANY_EA_WRREQS_STALL[20]	TCC_WRITE[20]	TCC_RW_REQ[21]	TCC_TOO_MANY_EA_WRREQS_STALL[21]	TCC_WRITE[21]	TCC_RW_REQ[22]	TCC_TOO_MANY_EA_WRREQS_STALL[22]	TCC_WRITE[22]	TCC_RW_REQ[23]	TCC_TOO_MANY_EA_WRREQS_STALL[23]	TCC_WRITE[23]	TCC_RW_REQ[24]	TCC_TOO_MANY_EA_WRREQS_STALL[24]	TCC_WRITE[24]	TCC_RW_REQ[25]	TCC_TOO_MANY_EA_WRREQS_STALL[25]	TCC_WRITE[25]	TCC_RW_REQ[26]	TCC_TOO_MANY_EA_WRREQS_STALL[26]	TCC_WRITE[26]	TCC_RW_REQ[27]	TCC_TOO_MANY_EA_WRREQS_STALL[27]	TCC_WRITE[27]	TCC_RW_REQ[28]	TCC_TOO_MANY_EA_WRREQS_STALL[28]	TCC_WRITE[28]	TCC_RW_REQ[29]	TCC_TOO_MANY_EA_WRREQS_STALL[29]	TCC_WRITE[29]	TCC_RW_REQ[30]	TCC_TOO_MANY_EA_WRREQS_STALL[30]	TCC_WRITE[30]	TCC_RW_REQ[31]	TCC_TOO_MANY_EA_WRREQS_STALL[31]	TCC_WRITE[31]	wave_size_4	obj_4	SQC_TC_DATA_WRITE_REQ	SQC_TC_DATA_ATOMIC_REQ	SQC_TC_STALL	SQC_TC_REQ	SQC_DCACHE_REQ_READ_16	SQC_ICACHE_REQ	SQC_ICACHE_HITS	SQC_ICACHE_MISSES	wave_size_5	obj_5	SQ_INSTS_VALU_INT64	SQ_INSTS_SMEM	SQ_INSTS_FLAT	SQ_INSTS_LDS	SQ_INSTS_GDS	SQ_INSTS_EXP_GDS	SQ_INSTS_BRANCH	SQ_INSTS_SENDMSG	TCP_TOTAL_ATOMIC_WITH_RET_sum	TCP_TOTAL_ATOMIC_WITHOUT_RET_sum	TCP_TOTAL_WRITEBACK_INVALIDATES_sum	TCP_TOTAL_CACHE_ACCESSES_sum	TA_BUFFER_COALESCED_READ_CYCLES_sum	TA_BUFFER_COALESCED_WRITE_CYCLES_sum	TD_COALESCABLE_WAVEFRONT_sum	SPI_RA_RES_STALL_CSN	SPI_RA_TMP_STALL_CSN	CPC_CPC_UTCL2IU_BUSY	CPC_CPC_UTCL2IU_IDLE	CPF_CMP_UTCL1_STALL_ON_TRANSLATION	TCC_READ_sum	TCC_WRITE_sum	TCC_ATOMIC_sum	TCC_WRITEBACK_sum	wave_size_6	obj_6	TCC_ATOMIC[0]	TCC_CYCLE[0]	TCC_EA_ATOMIC[0]	TCC_EA_ATOMIC_LEVEL[0]	TCC_ATOMIC[1]	TCC_CYCLE[1]	TCC_EA_ATOMIC[1]	TCC_EA_ATOMIC_LEVEL[1]	TCC_ATOMIC[2]	TCC_CYCLE[2]	TCC_EA_ATOMIC[2]	TCC_EA_ATOMIC_LEVEL[2]	TCC_ATOMIC[3]	TCC_CYCLE[3]	TCC_EA_ATOMIC[3]	TCC_EA_ATOMIC_LEVEL[3]	TCC_ATOMIC[4]	TCC_CYCLE[4]	TCC_EA_ATOMIC[4]	TCC_EA_ATOMIC_LEVEL[4]	TCC_ATOMIC[5]	TCC_CYCLE[5]	TCC_EA_ATOMIC[5]	TCC_EA_ATOMIC_LEVEL[5]	TCC_ATOMIC[6]	TCC_CYCLE[6]	TCC_EA_ATOMIC[6]	TCC_EA_ATOMIC_LEVEL[6]	TCC_ATOMIC[7]	TCC_CYCLE[7]	TCC_EA_ATOMIC[7]	TCC_EA_ATOMIC_LEVEL[7]	TCC_ATOMIC[8]	TCC_CYCLE[8]	TCC_EA_ATOMIC[8]	TCC_EA_ATOMIC_LEVEL[8]	TCC_ATOMIC[9]	TCC_CYCLE[9]	TCC_EA_ATOMIC[9]	TCC_EA_ATOMIC_LEVEL[9]	TCC_ATOMIC[10]	TCC_CYCLE[10]	TCC_EA_ATOMIC[10]	TCC_EA_ATOMIC_LEVEL[10]	TCC_ATOMIC[11]	TCC_CYCLE[11]	TCC_EA_ATOMIC[11]	TCC_EA_ATOMIC_LEVEL[11]	TCC_ATOMIC[12]	TCC_CYCLE[12]	TCC_EA_ATOMIC[12]	TCC_EA_ATOMIC_LEVEL[12]	TCC_ATOMIC[13]	TCC_CYCLE[13]	TCC_EA_ATOMIC[13]	TCC_EA_ATOMIC_LEVEL[13]	TCC_ATOMIC[14]	TCC_CYCLE[14]	TCC_EA_ATOMIC[14]	TCC_EA_ATOMIC_LEVEL[14]	TCC_ATOMIC[15]	TCC_CYCLE[15]	TCC_EA_ATOMIC[15]	TCC_EA_ATOMIC_LEVEL[15]	TCC_ATOMIC[16]	TCC_CYCLE[16]	TCC_EA_ATOMIC[16]	TCC_EA_ATOMIC_LEVEL[16]	TCC_ATOMIC[17]	TCC_CYCLE[17]	TCC_EA_ATOMIC[17]	TCC_EA_ATOMIC_LEVEL[17]	TCC_ATOMIC[18]	TCC_CYCLE[18]	TCC_EA_ATOMIC[18]	TCC_EA_ATOMIC_LEVEL[18]	TCC_ATOMIC[19]	TCC_CYCLE[19]	TCC_EA_ATOMIC[19]	TCC_EA_ATOMIC_LEVEL[19]	TCC_ATOMIC[20]	TCC_CYCLE[20]	TCC_EA_ATOMIC[20]	TCC_EA_ATOMIC_LEVEL[20]	TCC_ATOMIC[21]	TCC_CYCLE[21]	TCC_EA_ATOMIC[21]	TCC_EA_ATOMIC_LEVEL[21]	TCC_ATOMIC[22]	TCC_CYCLE[22]	TCC_EA_ATOMIC[22]	TCC_EA_ATOMIC_LEVEL[22]	TCC_ATOMIC[23]	TCC_CYCLE[23]	TCC_EA_ATOMIC[23]	TCC_EA_ATOMIC_LEVEL[23]	TCC_ATOMIC[24]	TCC_CYCLE[24]	TCC_EA_ATOMIC[24]	TCC_EA_ATOMIC_LEVEL[24]	TCC_ATOMIC[25]	TCC_CYCLE[25]	TCC_EA_ATOMIC[25]	TCC_EA_ATOMIC_LEVEL[25]	TCC_ATOMIC[26]	TCC_CYCLE[26]	TCC_EA_ATOMIC[26]	TCC_EA_ATOMIC_LEVEL[26]	TCC_ATOMIC[27]	TCC_CYCLE[27]	TCC_EA_ATOMIC[27]	TCC_EA_ATOMIC_LEVEL[27]	TCC_ATOMIC[28]	TCC_CYCLE[28]	TCC_EA_ATOMIC[28]	TCC_EA_ATOMIC_LEVEL[28]	TCC_ATOMIC[29]	TCC_CYCLE[29]	TCC_EA_ATOMIC[29]	TCC_EA_ATOMIC_LEVEL[29]	TCC_ATOMIC[30]	TCC_CYCLE[30]	TCC_EA_ATOMIC[30]	TCC_EA_ATOMIC_LEVEL[30]	TCC_ATOMIC[31]	TCC_CYCLE[31]	TCC_EA_ATOMIC[31]	TCC_EA_ATOMIC_LEVEL[31]	wave_size_7	obj_7	TCC_EA_RDREQ_IO_CREDIT_STALL[0]	TCC_EA_RDREQ_LEVEL[0]	TCC_EA_WRREQ[0]	TCC_EA_WRREQ_64B[0]	TCC_EA_RDREQ_IO_CREDIT_STALL[1]	TCC_EA_RDREQ_LEVEL[1]	TCC_EA_WRREQ[1]	TCC_EA_WRREQ_64B[1]	TCC_EA_RDREQ_IO_CREDIT_STALL[2]	TCC_EA_RDREQ_LEVEL[2]	TCC_EA_WRREQ[2]	TCC_EA_WRREQ_64B[2]	TCC_EA_RDREQ_IO_CREDIT_STALL[3]	TCC_EA_RDREQ_LEVEL[3]	TCC_EA_WRREQ[3]	TCC_EA_WRREQ_64B[3]	TCC_EA_RDREQ_IO_CREDIT_STALL[4]	TCC_EA_RDREQ_LEVEL[4]	TCC_EA_WRREQ[4]	TCC_EA_WRREQ_64B[4]	TCC_EA_RDREQ_IO_CREDIT_STALL[5]	TCC_EA_RDREQ_LEVEL[5]	TCC_EA_WRREQ[5]	TCC_EA_WRREQ_64B[5]	TCC_EA_RDREQ_IO_CREDIT_STALL[6]	TCC_EA_RDREQ_LEVEL[6]	TCC_EA_WRREQ[6]	TCC_EA_WRREQ_64B[6]	TCC_EA_RDREQ_IO_CREDIT_STALL[7]	TCC_EA_RDREQ_LEVEL[7]	TCC_EA_WRREQ[7]	TCC_EA_WRREQ_64B[7]	TCC_EA_RDREQ_IO_CREDIT_STALL[8]	TCC_EA_RDREQ_LEVEL[8]	TCC_EA_WRREQ[8]	TCC_EA_WRREQ_64B[8]	TCC_EA_RDREQ_IO_CREDIT_STALL[9]	TCC_EA_RDREQ_LEVEL[9]	TCC_EA_WRREQ[9]	TCC_EA_WRREQ_64B[9]	TCC_EA_RDREQ_IO_CREDIT_STALL[10]	TCC_EA_RDREQ_LEVEL[10]	TCC_EA_WRREQ[10]	TCC_EA_WRREQ_64B[10]	TCC_EA_RDREQ_IO_CREDIT_STALL[11]	TCC_EA_RDREQ_LEVEL[11]	TCC_EA_WRREQ[11]	TCC_EA_WRREQ_64B[11]	TCC_EA_RDREQ_IO_CREDIT_STALL[12]	TCC_EA_RDREQ_LEVEL[12]	TCC_EA_WRREQ[12]	TCC_EA_WRREQ_64B[12]	TCC_EA_RDREQ_IO_CREDIT_STALL[13]	TCC_EA_RDREQ_LEVEL[13]	TCC_EA_WRREQ[13]	TCC_EA_WRREQ_64B[13]	TCC_EA_RDREQ_IO_CREDIT_STALL[14]	TCC_EA_RDREQ_LEVEL[14]	TCC_EA_WRREQ[14]	TCC_EA_WRREQ_64B[14]	TCC_EA_RDREQ_IO_CREDIT_STALL[15]	TCC_EA_RDREQ_LEVEL[15]	TCC_EA_WRREQ[15]	TCC_EA_WRREQ_64B[15]	TCC_EA_RDREQ_IO_CREDIT_STALL[16]	TCC_EA_RDREQ_LEVEL[16]	TCC_EA_WRREQ[16]	TCC_EA_WRREQ_64B[16]	TCC_EA_RDREQ_IO_CREDIT_STALL[17]	TCC_EA_RDREQ_LEVEL[17]	TCC_EA_WRREQ[17]	TCC_EA_WRREQ_64B[17]	TCC_EA_RDREQ_IO_CREDIT_STALL[18]	TCC_EA_RDREQ_LEVEL[18]	TCC_EA_WRREQ[18]	TCC_EA_WRREQ_64B[18]	TCC_EA_RDREQ_IO_CREDIT_STALL[19]	TCC_EA_RDREQ_LEVEL[19]	TCC_EA_WRREQ[19]	TCC_EA_WRREQ_64B[19]	TCC_EA_RDREQ_IO_CREDIT_STALL[20]	TCC_EA_RDREQ_LEVEL[20]	TCC_EA_WRREQ[20]	TCC_EA_WRREQ_64B[20]	TCC_EA_RDREQ_IO_CREDIT_STALL[21]	TCC_EA_RDREQ_LEVEL[21]	TCC_EA_WRREQ[21]	TCC_EA_WRREQ_64B[21]	TCC_EA_RDREQ_IO_CREDIT_STALL[22]	TCC_EA_RDREQ_LEVEL[22]	TCC_EA_WRREQ[22]	TCC_EA_WRREQ_64B[22]	TCC_EA_RDREQ_IO_CREDIT_STALL[23]	TCC_EA_RDREQ_LEVEL[23]	TCC_EA_WRREQ[23]	TCC_EA_WRREQ_64B[23]	TCC_EA_RDREQ_IO_CREDIT_STALL[24]	TCC_EA_RDREQ_LEVEL[24]	TCC_EA_WRREQ[24]	TCC_EA_WRREQ_64B[24]	TCC_EA_RDREQ_IO_CREDIT_STALL[25]	TCC_EA_RDREQ_LEVEL[25]	TCC_EA_WRREQ[25]	TCC_EA_WRREQ_64B[25]	TCC_EA_RDREQ_IO_CREDIT_STALL[26]	TCC_EA_RDREQ_LEVEL[26]	TCC_EA_WRREQ[26]	TCC_EA_WRREQ_64B[26]	TCC_EA_RDREQ_IO_CREDIT_STALL[27]	TCC_EA_RDREQ_LEVEL[27]	TCC_EA_WRREQ[27]	TCC_EA_WRREQ_64B[27]	TCC_EA_RDREQ_IO_CREDIT_STALL[28]	TCC_EA_RDREQ_LEVEL[28]	TCC_EA_WRREQ[28]	TCC_EA_WRREQ_64B[28]	TCC_EA_RDREQ_IO_CREDIT_STALL[29]	TCC_EA_RDREQ_LEVEL[29]	TCC_EA_WRREQ[29]	TCC_EA_WRREQ_64B[29]	TCC_EA_RDREQ_IO_CREDIT_STALL[30]	TCC_EA_RDREQ_LEVEL[30]	TCC_EA_WRREQ[30]	TCC_EA_WRREQ_64B[30]	TCC_EA_RDREQ_IO_CREDIT_STALL[31]	TCC_EA_RDREQ_LEVEL[31]	TCC_EA_WRREQ[31]	TCC_EA_WRREQ_64B[31]	wave_size_8	obj_8	TCC_EA_RDREQ[0]	TCC_EA_RDREQ_32B[0]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]	TCC_EA_RDREQ_GMI_CREDIT_STALL[0]	TCC_EA_RDREQ[1]	TCC_EA_RDREQ_32B[1]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]	TCC_EA_RDREQ_GMI_CREDIT_STALL[1]	TCC_EA_RDREQ[2]	TCC_EA_RDREQ_32B[2]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]	TCC_EA_RDREQ_GMI_CREDIT_STALL[2]	TCC_EA_RDREQ[3]	TCC_EA_RDREQ_32B[3]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]	TCC_EA_RDREQ_GMI_CREDIT_STALL[3]	TCC_EA_RDREQ[4]	TCC_EA_RDREQ_32B[4]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]	TCC_EA_RDREQ_GMI_CREDIT_STALL[4]	TCC_EA_RDREQ[5]	TCC_EA_RDREQ_32B[5]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]	TCC_EA_RDREQ_GMI_CREDIT_STALL[5]	TCC_EA_RDREQ[6]	TCC_EA_RDREQ_32B[6]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]	TCC_EA_RDREQ_GMI_CREDIT_STALL[6]	TCC_EA_RDREQ[7]	TCC_EA_RDREQ_32B[7]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]	TCC_EA_RDREQ_GMI_CREDIT_STALL[7]	TCC_EA_RDREQ[8]	TCC_EA_RDREQ_32B[8]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]	TCC_EA_RDREQ_GMI_CREDIT_STALL[8]	TCC_EA_RDREQ[9]	TCC_EA_RDREQ_32B[9]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]	TCC_EA_RDREQ_GMI_CREDIT_STALL[9]	TCC_EA_RDREQ[10]	TCC_EA_RDREQ_32B[10]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]	TCC_EA_RDREQ_GMI_CREDIT_STALL[10]	TCC_EA_RDREQ[11]	TCC_EA_RDREQ_32B[11]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]	TCC_EA_RDREQ_GMI_CREDIT_STALL[11]	TCC_EA_RDREQ[12]	TCC_EA_RDREQ_32B[12]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]	TCC_EA_RDREQ_GMI_CREDIT_STALL[12]	TCC_EA_RDREQ[13]	TCC_EA_RDREQ_32B[13]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]	TCC_EA_RDREQ_GMI_CREDIT_STALL[13]	TCC_EA_RDREQ[14]	TCC_EA_RDREQ_32B[14]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]	TCC_EA_RDREQ_GMI_CREDIT_STALL[14]	TCC_EA_RDREQ[15]	TCC_EA_RDREQ_32B[15]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]	TCC_EA_RDREQ_GMI_CREDIT_STALL[15]	TCC_EA_RDREQ[16]	TCC_EA_RDREQ_32B[16]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]	TCC_EA_RDREQ_GMI_CREDIT_STALL[16]	TCC_EA_RDREQ[17]	TCC_EA_RDREQ_32B[17]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]	TCC_EA_RDREQ_GMI_CREDIT_STALL[17]	TCC_EA_RDREQ[18]	TCC_EA_RDREQ_32B[18]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]	TCC_EA_RDREQ_GMI_CREDIT_STALL[18]	TCC_EA_RDREQ[19]	TCC_EA_RDREQ_32B[19]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]	TCC_EA_RDREQ_GMI_CREDIT_STALL[19]	TCC_EA_RDREQ[20]	TCC_EA_RDREQ_32B[20]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]	TCC_EA_RDREQ_GMI_CREDIT_STALL[20]	TCC_EA_RDREQ[21]	TCC_EA_RDREQ_32B[21]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]	TCC_EA_RDREQ_GMI_CREDIT_STALL[21]	TCC_EA_RDREQ[22]	TCC_EA_RDREQ_32B[22]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]	TCC_EA_RDREQ_GMI_CREDIT_STALL[22]	TCC_EA_RDREQ[23]	TCC_EA_RDREQ_32B[23]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]	TCC_EA_RDREQ_GMI_CREDIT_STALL[23]	TCC_EA_RDREQ[24]	TCC_EA_RDREQ_32B[24]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]	TCC_EA_RDREQ_GMI_CREDIT_STALL[24]	TCC_EA_RDREQ[25]	TCC_EA_RDREQ_32B[25]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]	TCC_EA_RDREQ_GMI_CREDIT_STALL[25]	TCC_EA_RDREQ[26]	TCC_EA_RDREQ_32B[26]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]	TCC_EA_RDREQ_GMI_CREDIT_STALL[26]	TCC_EA_RDREQ[27]	TCC_EA_RDREQ_32B[27]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]	TCC_EA_RDREQ_GMI_CREDIT_STALL[27]	TCC_EA_RDREQ[28]	TCC_EA_RDREQ_32B[28]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]	TCC_EA_RDREQ_GMI_CREDIT_STALL[28]	TCC_EA_RDREQ[29]	TCC_EA_RDREQ_32B[29]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]	TCC_EA_RDREQ_GMI_CREDIT_STALL[29]	TCC_EA_RDREQ[30]	TCC_EA_RDREQ_32B[30]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]	TCC_EA_RDREQ_GMI_CREDIT_STALL[30]	TCC_EA_RDREQ[31]	TCC_EA_RDREQ_32B[31]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]	TCC_EA_RDREQ_GMI_CREDIT_STALL[31]	wave_size_9	obj_9	SQ_INSTS_VSKIPPED	SQ_INSTS	SQ_INSTS_VALU	SQ_INSTS_VALU_ADD_F16	SQ_INSTS_VALU_MUL_F16	SQ_INSTS_VALU_FMA_F16	SQ_INSTS_VALU_TRANS_F16	SQ_INSTS_VALU_ADD_F32	GRBM_SPI_BUSY	TCP_READ_TAGCONFLICT_STALL_CYCLES_sum	TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum	TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum	TCP_TA_TCP_STATE_READ_sum	TA_BUFFER_READ_WAVEFRONTS_sum	TA_BUFFER_WRITE_WAVEFRONTS_sum	TD_SPI_STALL_sum	TD_LOAD_WAVEFRONT_sum	SPI_CSN_NUM_THREADGROUPS	SPI_CSN_WAVE	CPC_CPC_TCIU_BUSY	CPC_CPC_TCIU_IDLE	CPF_CPF_TCIU_BUSY	CPF_CPF_TCIU_STALL	TCC_NC_REQ_sum	TCC_UC_REQ_sum	TCC_CC_REQ_sum	TCC_RW_REQ_sum	wave_size_10	obj_10	TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]	TCC_EA_WRREQ_GMI_CREDIT_STALL[0]	TCC_EA_WRREQ_IO_CREDIT_STALL[0]	TCC_EA_WRREQ_LEVEL[0]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]	TCC_EA_WRREQ_GMI_CREDIT_STALL[1]	TCC_EA_WRREQ_IO_CREDIT_STALL[1]	TCC_EA_WRREQ_LEVEL[1]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]	TCC_EA_WRREQ_GMI_CREDIT_STALL[2]	TCC_EA_WRREQ_IO_CREDIT_STALL[2]	TCC_EA_WRREQ_LEVEL[2]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]	TCC_EA_WRREQ_GMI_CREDIT_STALL[3]	TCC_EA_WRREQ_IO_CREDIT_STALL[3]	TCC_EA_WRREQ_LEVEL[3]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]	TCC_EA_WRREQ_GMI_CREDIT_STALL[4]	TCC_EA_WRREQ_IO_CREDIT_STALL[4]	TCC_EA_WRREQ_LEVEL[4]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]	TCC_EA_WRREQ_GMI_CREDIT_STALL[5]	TCC_EA_WRREQ_IO_CREDIT_STALL[5]	TCC_EA_WRREQ_LEVEL[5]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]	TCC_EA_WRREQ_GMI_CREDIT_STALL[6]	TCC_EA_WRREQ_IO_CREDIT_STALL[6]	TCC_EA_WRREQ_LEVEL[6]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]	TCC_EA_WRREQ_GMI_CREDIT_STALL[7]	TCC_EA_WRREQ_IO_CREDIT_STALL[7]	TCC_EA_WRREQ_LEVEL[7]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]	TCC_EA_WRREQ_GMI_CREDIT_STALL[8]	TCC_EA_WRREQ_IO_CREDIT_STALL[8]	TCC_EA_WRREQ_LEVEL[8]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]	TCC_EA_WRREQ_GMI_CREDIT_STALL[9]	TCC_EA_WRREQ_IO_CREDIT_STALL[9]	TCC_EA_WRREQ_LEVEL[9]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]	TCC_EA_WRREQ_GMI_CREDIT_STALL[10]	TCC_EA_WRREQ_IO_CREDIT_STALL[10]	TCC_EA_WRREQ_LEVEL[10]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]	TCC_EA_WRREQ_GMI_CREDIT_STALL[11]	TCC_EA_WRREQ_IO_CREDIT_STALL[11]	TCC_EA_WRREQ_LEVEL[11]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]	TCC_EA_WRREQ_GMI_CREDIT_STALL[12]	TCC_EA_WRREQ_IO_CREDIT_STALL[12]	TCC_EA_WRREQ_LEVEL[12]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]	TCC_EA_WRREQ_GMI_CREDIT_STALL[13]	TCC_EA_WRREQ_IO_CREDIT_STALL[13]	TCC_EA_WRREQ_LEVEL[13]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]	TCC_EA_WRREQ_GMI_CREDIT_STALL[14]	TCC_EA_WRREQ_IO_CREDIT_STALL[14]	TCC_EA_WRREQ_LEVEL[14]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]	TCC_EA_WRREQ_GMI_CREDIT_STALL[15]	TCC_EA_WRREQ_IO_CREDIT_STALL[15]	TCC_EA_WRREQ_LEVEL[15]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]	TCC_EA_WRREQ_GMI_CREDIT_STALL[16]	TCC_EA_WRREQ_IO_CREDIT_STALL[16]	TCC_EA_WRREQ_LEVEL[16]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]	TCC_EA_WRREQ_GMI_CREDIT_STALL[17]	TCC_EA_WRREQ_IO_CREDIT_STALL[17]	TCC_EA_WRREQ_LEVEL[17]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]	TCC_EA_WRREQ_GMI_CREDIT_STALL[18]	TCC_EA_WRREQ_IO_CREDIT_STALL[18]	TCC_EA_WRREQ_LEVEL[18]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]	TCC_EA_WRREQ_GMI_CREDIT_STALL[19]	TCC_EA_WRREQ_IO_CREDIT_STALL[19]	TCC_EA_WRREQ_LEVEL[19]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]	TCC_EA_WRREQ_GMI_CREDIT_STALL[20]	TCC_EA_WRREQ_IO_CREDIT_STALL[20]	TCC_EA_WRREQ_LEVEL[20]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]	TCC_EA_WRREQ_GMI_CREDIT_STALL[21]	TCC_EA_WRREQ_IO_CREDIT_STALL[21]	TCC_EA_WRREQ_LEVEL[21]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]	TCC_EA_WRREQ_GMI_CREDIT_STALL[22]	TCC_EA_WRREQ_IO_CREDIT_STALL[22]	TCC_EA_WRREQ_LEVEL[22]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]	TCC_EA_WRREQ_GMI_CREDIT_STALL[23]	TCC_EA_WRREQ_IO_CREDIT_STALL[23]	TCC_EA_WRREQ_LEVEL[23]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]	TCC_EA_WRREQ_GMI_CREDIT_STALL[24]	TCC_EA_WRREQ_IO_CREDIT_STALL[24]	TCC_EA_WRREQ_LEVEL[24]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]	TCC_EA_WRREQ_GMI_CREDIT_STALL[25]	TCC_EA_WRREQ_IO_CREDIT_STALL[25]	TCC_EA_WRREQ_LEVEL[25]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]	TCC_EA_WRREQ_GMI_CREDIT_STALL[26]	TCC_EA_WRREQ_IO_CREDIT_STALL[26]	TCC_EA_WRREQ_LEVEL[26]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]	TCC_EA_WRREQ_GMI_CREDIT_STALL[27]	TCC_EA_WRREQ_IO_CREDIT_STALL[27]	TCC_EA_WRREQ_LEVEL[27]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]	TCC_EA_WRREQ_GMI_CREDIT_STALL[28]	TCC_EA_WRREQ_IO_CREDIT_STALL[28]	TCC_EA_WRREQ_LEVEL[28]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]	TCC_EA_WRREQ_GMI_CREDIT_STALL[29]	TCC_EA_WRREQ_IO_CREDIT_STALL[29]	TCC_EA_WRREQ_LEVEL[29]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]	TCC_EA_WRREQ_GMI_CREDIT_STALL[30]	TCC_EA_WRREQ_IO_CREDIT_STALL[30]	TCC_EA_WRREQ_LEVEL[30]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]	TCC_EA_WRREQ_GMI_CREDIT_STALL[31]	TCC_EA_WRREQ_IO_CREDIT_STALL[31]	TCC_EA_WRREQ_LEVEL[31]	wave_size_11	obj_11	SQC_DCACHE_REQ_READ_1	SQC_DCACHE_REQ_READ_2	SQC_DCACHE_REQ_READ_4	wave_size_12	obj_12	SQ_CYCLES	SQ_BUSY_CYCLES	SQ_WAVES	SQ_INSTS_VALU_CVT	SQ_INSTS_VMEM_WR	SQ_INSTS_VMEM_RD	SQ_INSTS_VMEM	SQ_INSTS_SALU	GRBM_COUNT	GRBM_GUI_ACTIVE	TCP_GATE_EN1_sum	TCP_GATE_EN2_sum	TCP_TD_TCP_STALL_CYCLES_sum	TCP_TCR_TCP_STALL_CYCLES_sum	TA_TA_BUSY_sum	TA_BUFFER_WAVEFRONTS_sum	TD_TD_BUSY_sum	TD_TC_STALL_sum	SPI_CSN_WINDOW_VALID	SPI_CSN_BUSY	CPC_CPC_STAT_BUSY	CPC_CPC_STAT_IDLE	CPF_CPF_STAT_BUSY	CPF_CPF_STAT_STALL	TCC_CYCLE_sum	TCC_BUSY_sum	TCC_PROBE_sum	TCC_PROBE_ALL_sum	wave_size_13	obj_13	SQ_THREAD_CYCLES_VALU	SQ_IFETCH	SQ_LDS_BANK_CONFLICT	SQ_LDS_ADDR_CONFLICT	SQ_LDS_UNALIGNED_STALL	SQ_WAVES_EQ_64	SQ_WAVES_LT_64	SQ_WAVES_LT_48	TCP_TCC_WRITE_REQ_sum	TCP_TCC_ATOMIC_WITH_RET_REQ_sum	TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum	TCP_TCC_NC_READ_REQ_sum	TA_FLAT_WAVEFRONTS_sum	TA_FLAT_READ_WAVEFRONTS_sum	SPI_RA_BAR_CU_FULL_CSN	SPI_RA_TGLIM_CU_FULL_CSN	TCC_EA_RDREQ_DRAM_sum	TCC_TAG_STALL_sum	TCC_NORMAL_WRITEBACK_sum	TCC_ALL_TC_OP_WB_WRITEBACK_sum	wave_size_14	obj_14	SQ_INSTS_FLAT_LDS_ONLY	SQ_INSTS_VALU_MFMA_MOPS_I8	SQ_INSTS_VALU_MFMA_MOPS_F16	SQ_INSTS_VALU_MFMA_MOPS_BF16	SQ_INSTS_VALU_MFMA_MOPS_F32	SQ_INSTS_VALU_MFMA_MOPS_F64	SQC_TC_INST_REQ	SQC_TC_DATA_READ_REQ	TCP_TCC_RW_READ_REQ_sum	TCP_TCC_RW_WRITE_REQ_sum	TCP_TCC_RW_ATOMIC_REQ_sum	TCP_PENDING_STALL_CYCLES_sum	wave_size_15	obj_15	SQC_ICACHE_MISSES_DUPLICATE	SQC_DCACHE_INPUT_VALID_READYB	SQC_DCACHE_ATOMIC	SQC_DCACHE_REQ_READ_8	SQC_DCACHE_REQ	SQC_DCACHE_HITS	SQC_DCACHE_MISSES	SQC_DCACHE_MISSES_DUPLICATE	wave_size_16	obj_16	SQ_ACTIVE_INST_SCA	SQ_ACTIVE_INST_EXP_GDS	SQ_ACTIVE_INST_MISC	SQ_ACTIVE_INST_FLAT	SQ_INST_CYCLES_VMEM_WR	SQ_INST_CYCLES_VMEM_RD	SQ_INST_CYCLES_SMEM	SQ_INST_CYCLES_SALU	TCP_TCP_LATENCY_sum	TCP_TCC_READ_REQ_LATENCY_sum	TCP_TCC_WRITE_REQ_LATENCY_sum	TCP_TCC_READ_REQ_sum	TA_ADDR_STALLED_BY_TD_CYCLES_sum	TA_DATA_STALLED_BY_TC_CYCLES_sum	SPI_RA_SGPR_SIMD_FULL_CSN	SPI_RA_LDS_CU_FULL_CSN	CPC_ME1_DC0_SPI_BUSY	TCC_EA_WRREQ_STALL_sum	TCC_EA_RDREQ_sum	TCC_EA_RDREQ_32B_sum	TCC_EA_RD_UNCACHED_32B_sum	wave_size_17	obj_17	SQ_INSTS_SMEM_NORM	SQ_INSTS_MFMA	SQ_INSTS_VALU_MFMA_I8	SQ_INSTS_VALU_MFMA_F16	SQ_INSTS_VALU_MFMA_BF16	SQ_INSTS_VALU_MFMA_F32	SQ_INSTS_VALU_MFMA_F64	SQ_VALU_MFMA_BUSY_CYCLES	TCP_TCC_UC_ATOMIC_REQ_sum	TCP_TCC_CC_READ_REQ_sum	TCP_TCC_CC_WRITE_REQ_sum	TCP_TCC_CC_ATOMIC_REQ_sum	SPI_VWC_CSC_WR	SPI_RA_BULKY_CU_FULL_CSN	TCC_EA_RDREQ_LEVEL_sum	TCC_EA_WRREQ_LEVEL_sum	TCC_EA_ATOMIC_LEVEL_sum	wave_size_18	obj_18	TCC_HIT[0]	TCC_MISS[0]	TCC_READ[0]	TCC_REQ[0]	TCC_HIT[1]	TCC_MISS[1]	TCC_READ[1]	TCC_REQ[1]	TCC_HIT[2]	TCC_MISS[2]	TCC_READ[2]	TCC_REQ[2]	TCC_HIT[3]	TCC_MISS[3]	TCC_READ[3]	TCC_REQ[3]	TCC_HIT[4]	TCC_MISS[4]	TCC_READ[4]	TCC_REQ[4]	TCC_HIT[5]	TCC_MISS[5]	TCC_READ[5]	TCC_REQ[5]	TCC_HIT[6]	TCC_MISS[6]	TCC_READ[6]	TCC_REQ[6]	TCC_HIT[7]	TCC_MISS[7]	TCC_READ[7]	TCC_REQ[7]	TCC_HIT[8]	TCC_MISS[8]	TCC_READ[8]	TCC_REQ[8]	TCC_HIT[9]	TCC_MISS[9]	TCC_READ[9]	TCC_REQ[9]	TCC_HIT[10]	TCC_MISS[10]	TCC_READ[10]	TCC_REQ[10]	TCC_HIT[11]	TCC_MISS[11]	TCC_READ[11]	TCC_REQ[11]	TCC_HIT[12]	TCC_MISS[12]	TCC_READ[12]	TCC_REQ[12]	TCC_HIT[13]	TCC_MISS[13]	TCC_READ[13]	TCC_REQ[13]	TCC_HIT[14]	TCC_MISS[14]	TCC_READ[14]	TCC_REQ[14]	TCC_HIT[15]	TCC_MISS[15]	TCC_READ[15]	TCC_REQ[15]	TCC_HIT[16]	TCC_MISS[16]	TCC_READ[16]	TCC_REQ[16]	TCC_HIT[17]	TCC_MISS[17]	TCC_READ[17]	TCC_REQ[17]	TCC_HIT[18]	TCC_MISS[18]	TCC_READ[18]	TCC_REQ[18]	TCC_HIT[19]	TCC_MISS[19]	TCC_READ[19]	TCC_REQ[19]	TCC_HIT[20]	TCC_MISS[20]	TCC_READ[20]	TCC_REQ[20]	TCC_HIT[21]	TCC_MISS[21]	TCC_READ[21]	TCC_REQ[21]	TCC_HIT[22]	TCC_MISS[22]	TCC_READ[22]	TCC_REQ[22]	TCC_HIT[23]	TCC_MISS[23]	TCC_READ[23]	TCC_REQ[23]	TCC_HIT[24]	TCC_MISS[24]	TCC_READ[24]	TCC_REQ[24]	TCC_HIT[25]	TCC_MISS[25]	TCC_READ[25]	TCC_REQ[25]	TCC_HIT[26]	TCC_MISS[26]	TCC_READ[26]	TCC_REQ[26]	TCC_HIT[27]	TCC_MISS[27]	TCC_READ[27]	TCC_REQ[27]	TCC_HIT[28]	TCC_MISS[28]	TCC_READ[28]	TCC_REQ[28]	TCC_HIT[29]	TCC_MISS[29]	TCC_READ[29]	TCC_REQ[29]	TCC_HIT[30]	TCC_MISS[30]	TCC_READ[30]	TCC_REQ[30]	TCC_HIT[31]	TCC_MISS[31]	TCC_READ[31]	TCC_REQ[31]	Start_Timestamp	End_Timestamp
2	1	vecCopy(double*, double*, double*, int, int)	2	1048576	256	0	0	8	0	16	64	0x7fafae7e8ec0	0	0	0	0	0	0	0	114688	2097152.0	2097152.0	1048576.0	1048576.0	0.0	0.0	0.0	16384.0	8528	18678	6328	550	0	21756	203809.0	0.0	72736.0	131073.0	64	0x7fc2dd45cec0	8860939	8418214	98661	344064	1390094	0	0	163840	0.0	524288.0	0.0	524288.0	127328.0	32768.0	280006	0	0	8319	92408.0	92408.0	0.0	92408.0	64	0x7f67fb880ec0	0	0	1048576	0	0	0	0	0	0.0	0.0	0.0	0.0	16384.0	0.0	0	32768	65550.0	0.0	0.0	0.0	64	0x7f1be8a7cec0	6379	0	4096	6404	0	4096	6329	0	4096	6380	0	4096	6351	0	4096	6387	0	4096	6388	0	4096	6387	0	4096	6385	0	4096	6379	0	4096	6403	0	4096	6333	0	4096	6375	0	4096	6357	0	4096	6385	0	4096	6394	0	4096	6376	0	4096	6415	0	4096	6372	0	4096	6405	0	4096	6373	0	4096	6349	0	4096	6383	0	4096	6348	0	4096	6349	0	4096	6374	0	4096	6419	0	4096	6372	0	4096	6413	0	4096	6374	0	4096	6350	0	4096	6384	0	4096	64	0x7fe215058ec0	0	0	0	56	0	65536	65536	0	64	0x7f923af74ec0	0	65536	32768	0	0	0	16384	16384	0.0	0.0	0.0	524288.0	0.0	0.0	0.0	5843	0	819	21683	0	73269.0	131072.0	0.0	46242.0	64	0x7faee6264ec0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	0	22576	0	0	64	0x7f3373cf8ec0	0	1070406	2872	2872	0	1355038	2900	2900	0	1235692	2896	2896	0	1330554	2896	2896	0	1272053	2924	2924	0	1225242	2880	2880	0	1069199	2924	2924	0	1249540	2864	2864	0	1242958	2864	2864	0	1136055	2868	2868	0	1216196	2896	2896	0	1199400	2900	2900	0	1292735	2892	2892	0	1197751	2924	2924	0	1165077	2872	2872	0	1569724	2920	2920	0	1384478	2848	2848	0	1249928	2924	2924	0	1204513	2852	2852	0	1309165	2912	2912	0	1392058	2880	2880	0	1301210	2888	2888	0	1198037	2848	2848	0	1499610	2872	2872	0	1150983	2866	2866	0	1135638	2852	2852	0	1617036	2924	2924	0	1195090	2856	2856	0	1532729	2912	2912	0	1230167	2880	2880	0	1248819	2888	2888	0	1320949	2852	2852	64	0x7f53820d4ec0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	31	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4097	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	64	0x7fe652204ec0	0	393216	163840	0	0	0	0	0	15953	0.0	0.0	0.0	32768.0	0.0	0.0	428.0	32768.0	4096	16384	302	22694	1286	0	56.0	0.0	0.0	203649.0	64	0x7f0eb4224ec0	0	0	0	932520	0	0	0	942446	0	0	0	883403	0	0	0	995686	0	0	0	999233	0	0	0	942774	0	0	0	882049	11	0	0	1077842	0	0	0	925990	0	0	0	869985	0	0	0	892724	0	0	0	934501	0	0	0	900272	8	0	0	1045353	0	0	0	1001744	0	0	0	989843	0	0	0	872030	0	0	0	1034514	0	0	0	892212	27	0	0	1133017	0	0	0	987952	0	0	0	1014360	0	0	0	943067	0	0	0	1014494	0	0	0	1022817	17	0	0	1032236	0	0	0	941043	0	0	0	949838	2	0	0	1099293	0	0	0	994135	0	0	0	1059857	0	0	0	943916	64	0x7fb3602b8ec0	32768	32768	0	64	0x7fc2ea4d4ec0	180672	110253	16384	0	16384	16384	32768	49152	22583	22583	1711520.0	1291155.0	3385.0	163871.0	955325.0	0.0	1282971.0	984804.0	178961	118388	22583	0	22583	0	722656.0	410389.0	0.0	0.0	64	0x7f6f850e8ec0	10485760	65536	0	0	0	16384	0	0	131072.0	0.0	0.0	0.0	32768.0	16384.0	0	0	131072.0	34755.0	46215.0	0.0	64	0x7fcaea368ec0	0	0	0	0	0	0	0	56	131072.0	131072.0	0.0	962608.0	64	0x7f33ba568ec0	0	55434	0	0	65536	63800	56	1680	64	0x7f084a7e8ec0	114688	0	32768	32768	16384	16384	65536	49152	27016783.0	85693015.0	39940578.0	131072.0	0.0	179709.0	0	0	12685	601.0	131073.0	0.0	0.0	64	0x7fc70d444ec0	131072	0	0	0	0	0	0	0	0.0	0.0	0.0	0.0	16384	0	40346123.0	32083541.0	0.0	64	0x7ffa6c820ec0	2266	4096	2266	6362	2245	4096	2245	6341	2312	4096	2312	6408	2319	4096	2319	6415	2246	4096	2246	6342	2225	4096	2225	6321	2300	4096	2300	6396	2329	4096	2329	6425	2333	4096	2333	6429	2267	4096	2267	6363	2250	4096	2250	6346	2304	4096	2304	6400	2325	4096	2325	6421	2248	4096	2248	6344	2228	4096	2228	6324	2301	4096	2301	6397	2276	4096	2276	6372	2272	4096	2272	6368	2262	4096	2262	6358	2273	4096	2273	6369	2389	4097	2390	6486	2271	4096	2271	6367	2232	4096	2232	6328	2223	4096	2223	6319	2222	4096	2222	6318	2275	4096	2275	6371	2272	4096	2272	6368	2261	4096	2261	6357	2278	4096	2278	6374	2337	4096	2337	6433	2275	4096	2275	6371	2235	4096	2235	6331	198394440082212	198394440098052