foreman
aa3989dcd0
SWDEV-172202 - Workaround the scheduler for systems don't support PCIe 3 atomics properly. The idea is the scheduler uses a device side global as write_index, and only write the write_index back to the hsa queue when the last thread of the scheduler leaves. This change along with the library side change have been tested on systems with or without proper PCIe 3 atomics support. Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocblit.cpp#29 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocsched.hpp#2 edit
74 рядки
3.5 KiB
C++
74 рядки
3.5 KiB
C++
//
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// Copyright (c) 2018 Advanced Micro Devices, Inc. All rights reserved.
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//
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#pragma once
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namespace roc {
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//! AmdAqlWrap slot state
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enum AqlWrapState {
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AQL_WRAP_FREE = 0,
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AQL_WRAP_RESERVED,
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AQL_WRAP_READY,
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AQL_WRAP_MARKER,
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AQL_WRAP_BUSY,
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AQL_WRAP_DONE
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};
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struct AmdVQueueHeader {
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uint32_t aql_slot_num; //!< [LRO/SRO] The total number of the AQL slots (multiple of 64).
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uint32_t event_slot_num; //!< [LRO] The number of kernel events in the events buffer
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uint64_t event_slot_mask; //!< [LRO] A pointer to the allocation bitmask array for the events
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uint64_t event_slots; //!< [LRO] Pointer to a buffer for the events.
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// Array of event_slot_num entries of AmdEvent
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uint64_t aql_slot_mask; //!< [LRO/SRO]A pointer to the allocation bitmask for aql_warp slots
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uint32_t command_counter; //!< [LRW] The global counter for the submitted commands into the queue
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uint32_t wait_size; //!< [LRO] The wait list size (in clk_event_t)
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uint32_t arg_size; //!< [LRO] The size of argument buffer (in bytes)
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uint32_t mask_groups; //!< Processed mask groups by one thread
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uint64_t kernel_table; //!< [LRO] Pointer to an array with all kernel objects (ulong for each entry)
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uint32_t reserved[2]; //!< For the future usage
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};
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struct AmdAqlWrap {
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uint32_t state; //!< [LRW/SRW] The current state of the AQL wrapper: FREE, RESERVED, READY,
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// MARKER, BUSY and DONE. The block could be returned back to a free state.
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uint32_t enqueue_flags; //!< [LWO/SRO] Contains the flags for the kernel execution start
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uint32_t command_id; //!< [LWO/SRO] The unique command ID
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uint32_t child_counter; //!< [LRW/SRW] Counter that determine the launches of child kernels.
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// Its incremented on the
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// start and decremented on the finish. The parent kernel can be considered as
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// done when the value is 0 and the state is DONE
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uint64_t completion; //!< [LWO/SRO] CL event for the current execution (clk_event_t)
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uint64_t parent_wrap; //!< [LWO/SRO] Pointer to the parent AQL wrapper (AmdAqlWrap*)
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uint64_t wait_list; //!< [LRO/SRO] Pointer to an array of clk_event_t objects (64 bytes default)
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uint32_t wait_num; //!< [LWO/SRO] The number of cl_event_wait objects
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uint32_t reserved[5]; //!< For the future usage
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hsa_kernel_dispatch_packet_t aql; //!< [LWO/SRO] AQL packet 64 bytes AQL packet
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};
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struct AmdEvent {
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uint32_t state; //!< [LRO/SRW] Event state: START, END, COMPLETE
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uint32_t counter; //!< [LRW] Event retain/release counter. 0 means the event is free
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uint64_t timer[3]; //!< [LRO/SWO] Timer values for profiling for each state
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uint64_t captureInfo; //!< [LRW/SRO] Profiling capture info for CLK_PROFILING_COMMAND_EXEC_TIME
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};
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struct SchedulerParam {
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uint64_t kernarg_address;
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uint64_t hidden_global_offset_x;
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uint64_t hidden_global_offset_y;
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uint64_t hidden_global_offset_z;
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uint64_t thread_counter;
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uint64_t child_queue;
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hsa_kernel_dispatch_packet_t scheduler_aql;
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hsa_signal_t complete_signal;
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uint64_t vqueue_header;
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uint32_t signal; //!< Signal to stop the child queue
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uint32_t eng_clk; //!< Engine clock in Mhz
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uint64_t parentAQL; //!< Host parent AmdAqlWrap packet
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uint64_t write_index; //!< Write Index to the child queue
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};
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}
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