foreman
9c877959f6
SWDEV-162389 - OpenCL Support for COMgr - currently COMgr library does not support gfx10+ - to build the OCL driver with the COMgr support, add an COMGR_DIR option for the MAKE command - the COMGR_DIR specifies the directory that contains the COMgr header file, "include/amd_comgr.h", and library, "lib/libamd_comgr.so" NOTE: check in the codes to unblock German's work for now, codes will be modified to handle HSAIL and LC paths dynamically. Affected files ... ... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/build/Makefile.api#176 edit ... //depot/stg/opencl/drivers/opencl/opencldefs#235 edit ... //depot/stg/opencl/drivers/opencl/runtime/build/Makefile.runtime#76 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/devprogram.cpp#12 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/devprogram.hpp#8 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/build/Makefile.oclrocm#21 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocdefs.hpp#20 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocprogram.cpp#94 edit
79 líneas
4.0 KiB
C++
79 líneas
4.0 KiB
C++
#pragma once
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#ifndef WITHOUT_HSA_BACKEND
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namespace roc {
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//! Alignment restriciton for the pinned memory
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const static size_t PinnedMemoryAlignment = 4 * Ki;
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//! Specific defines for images for Dynamic Parallelism
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const static uint DeviceQueueMaskSize = 32;
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typedef uint HsaDeviceId;
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struct AMDDeviceInfo {
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HsaDeviceId hsaDeviceId_; //!< Machine id
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const char* targetName_; //!< Target name for compilation
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const char* machineTarget_; //!< Machine target
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const char* machineTargetLC_;//!< Machine target for LC
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const char* complibTarget_; //!< Compiler library target name
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uint simdPerCU_; //!< Number of SIMDs per CU
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uint simdWidth_; //!< Number of workitems processed per SIMD
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uint simdInstructionWidth_; //!< Number of instructions processed per SIMD
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uint memChannelBankWidth_; //!< Memory channel bank width
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uint localMemSizePerCU_; //!< Local memory size per CU
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uint localMemBanks_; //!< Number of banks of local memory
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uint gfxipVersion_; //!< The core engine GFXIP version
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uint pciDeviceId_; //!< PCIe device id
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bool xnackEnabled_; //!< Enable XNACK feature
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};
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// The device ID must match with the device's index into DeviceInfo
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const HsaDeviceId HSA_SPECTRE_ID = 0;
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const HsaDeviceId HSA_SPOOKY_ID = 1;
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const HsaDeviceId HSA_TONGA_ID = 2;
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const HsaDeviceId HSA_CARRIZO_ID = 3;
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const HsaDeviceId HSA_ICELAND_ID = 4;
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const HsaDeviceId HSA_FIJI_ID = 5;
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const HsaDeviceId HSA_HAWAII_ID = 6;
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const HsaDeviceId HSA_ELLESMERE_ID = 7;
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const HsaDeviceId HSA_BAFFIN_ID = 8;
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const HsaDeviceId HSA_VEGA10_ID = 9;
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const HsaDeviceId HSA_VEGA10_HBCC_ID = 10;
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const HsaDeviceId HSA_RAVEN_ID = 11;
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const HsaDeviceId HSA_VEGA12_ID = 12;
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const HsaDeviceId HSA_VEGA20_ID = 13;
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const HsaDeviceId HSA_ARIEL_ID = 14;
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const HsaDeviceId HSA_NAVI10_ID = 15;
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const HsaDeviceId HSA_INVALID_DEVICE_ID = -1;
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static const AMDDeviceInfo DeviceInfo[] = {
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// targetName machineTarget
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/* TARGET_KAVERI_SPECTRE */ {HSA_SPECTRE_ID, "", "kaveri", "", "Spectre", 4, 16, 1, 256, 64 * Ki,
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32, 0, 0, false},
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/* TARGET_KAVERI_SPOOKY */ {HSA_SPOOKY_ID, "", "kaveri", "", "Spooky", 4, 16, 1, 256, 64 * Ki, 32,
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0, 0, false},
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/* TARGET_TONGA */ {HSA_TONGA_ID, "", "tonga", "gfx802", "Tonga", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET_CARRIZO */ {HSA_CARRIZO_ID, "", "carrizo", "", "Carrizo", 4, 16, 1, 256, 64 * Ki, 32, 0,
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0, true},
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/* TARGET_ICELAND */ {HSA_ICELAND_ID, "", "iceland", "gfx802", "Iceland", 4, 16, 1, 256, 64 * Ki, 32, 0,
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0, false},
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/* TARGET_FIJI */ {HSA_FIJI_ID, "", "fiji", "gfx803", "Fiji", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET HAWAII */ {HSA_HAWAII_ID, "", "hawaii", "", "Hawaii", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET ELLESMERE */ {HSA_ELLESMERE_ID, "", "polaris10", "gfx803", "Ellesmere", 4, 16, 1, 256, 64 * Ki,
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32, 0, 0, false},
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/* TARGET BAFFIN */ {HSA_BAFFIN_ID, "", "polaris11", "gfx803", "Baffin", 4, 16, 1, 256, 64 * Ki, 32, 0,
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0, false},
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/* TARGET VEGA10 */ {HSA_VEGA10_ID, "", "gfx900", "gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET VEGA10_HBCC */ {HSA_VEGA10_HBCC_ID, "", "gfx901", "gfx901", "gfx901", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET RAVEN */ {HSA_RAVEN_ID, "", "gfx902", "gfx902", "gfx902", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, true},
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/* TARGET VEGA12 */ {HSA_VEGA12_ID, "", "gfx904", "gfx904", "gfx904", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET VEGA20 */ {HSA_VEGA20_ID, "", "gfx906", "gfx906", "gfx906", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET ARIEL */ {HSA_ARIEL_ID, "", "gfx1000", "gfx1000", "gfx1000", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false},
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/* TARGET NAVI10 */ {HSA_NAVI10_ID, "", "gfx1010", "gfx1010", "gfx1010", 4, 16, 1, 256, 64 * Ki, 32, 0, 0, false}};
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}
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const uint kMaxAsyncQueues = 8; // set to match the number of pipes, which is 8
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#endif
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