German Andryeyev
5319163521
git-subtree-dir: projects/rocr-runtime/libhsakmt/include/impl git-subtree-mainline:55f7d39fa5git-subtree-split:c34ec1e52f
364 wiersze
14 KiB
C
364 wiersze
14 KiB
C
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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// This file is used only for open source cmake builds, if we hardcode the
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// register values in amd_aql_queue.cpp then this file won't be required. For
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// now we are using this file where register details are spelled out in the
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// structs/unions below.
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#ifndef _WSL_INC_REGISTERS_H_
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#define _WSL_INC_REGISTERS_H_
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typedef enum SQ_RSRC_BUF_TYPE {
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SQ_RSRC_BUF = 0x00000000,
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SQ_RSRC_BUF_RSVD_1 = 0x00000001,
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SQ_RSRC_BUF_RSVD_2 = 0x00000002,
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SQ_RSRC_BUF_RSVD_3 = 0x00000003,
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} SQ_RSRC_BUF_TYPE;
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typedef enum BUF_DATA_FORMAT {
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BUF_DATA_FORMAT_INVALID = 0x00000000,
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BUF_DATA_FORMAT_8 = 0x00000001,
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BUF_DATA_FORMAT_16 = 0x00000002,
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BUF_DATA_FORMAT_8_8 = 0x00000003,
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BUF_DATA_FORMAT_32 = 0x00000004,
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BUF_DATA_FORMAT_16_16 = 0x00000005,
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BUF_DATA_FORMAT_10_11_11 = 0x00000006,
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BUF_DATA_FORMAT_11_11_10 = 0x00000007,
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BUF_DATA_FORMAT_10_10_10_2 = 0x00000008,
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BUF_DATA_FORMAT_2_10_10_10 = 0x00000009,
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BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a,
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BUF_DATA_FORMAT_32_32 = 0x0000000b,
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BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c,
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BUF_DATA_FORMAT_32_32_32 = 0x0000000d,
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BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e,
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BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f,
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} BUF_DATA_FORMAT;
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typedef enum BUF_NUM_FORMAT {
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BUF_NUM_FORMAT_UNORM = 0x00000000,
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BUF_NUM_FORMAT_SNORM = 0x00000001,
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BUF_NUM_FORMAT_USCALED = 0x00000002,
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BUF_NUM_FORMAT_SSCALED = 0x00000003,
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BUF_NUM_FORMAT_UINT = 0x00000004,
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BUF_NUM_FORMAT_SINT = 0x00000005,
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BUF_NUM_FORMAT_SNORM_OGL__SI__CI = 0x00000006,
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BUF_NUM_FORMAT_RESERVED_6__VI = 0x00000006,
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BUF_NUM_FORMAT_FLOAT = 0x00000007,
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} BUF_NUM_FORMAT;
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typedef enum BUF_FORMAT {
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BUF_FORMAT_32_UINT = 0x00000014,
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} BUF_FORMAT;
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typedef enum SQ_SEL_XYZW01 {
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SQ_SEL_0 = 0x00000000,
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SQ_SEL_1 = 0x00000001,
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SQ_SEL_RESERVED_0 = 0x00000002,
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SQ_SEL_RESERVED_1 = 0x00000003,
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SQ_SEL_X = 0x00000004,
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SQ_SEL_Y = 0x00000005,
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SQ_SEL_Z = 0x00000006,
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SQ_SEL_W = 0x00000007,
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} SQ_SEL_XYZW01;
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union COMPUTE_TMPRING_SIZE {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int WAVES : 12;
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unsigned int WAVESIZE : 13;
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unsigned int : 7;
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#elif defined(BIGENDIAN_CPU)
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unsigned int : 7;
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unsigned int WAVESIZE : 13;
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unsigned int WAVES : 12;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union COMPUTE_TMPRING_SIZE_GFX11 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int WAVES : 12;
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unsigned int WAVESIZE : 15;
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unsigned int : 5;
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#elif defined(BIGENDIAN_CPU)
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unsigned int : 5;
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unsigned int WAVESIZE : 15;
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unsigned int WAVES : 12;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union COMPUTE_TMPRING_SIZE_GFX12 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int WAVES : 12;
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unsigned int WAVESIZE : 18;
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unsigned int : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int : 2;
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unsigned int WAVESIZE : 18;
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unsigned int WAVES : 12;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union SQ_BUF_RSRC_WORD0 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int BASE_ADDRESS : 32;
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#elif defined(BIGENDIAN_CPU)
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unsigned int BASE_ADDRESS : 32;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union SQ_BUF_RSRC_WORD1 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int BASE_ADDRESS_HI : 16;
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unsigned int STRIDE : 14;
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unsigned int CACHE_SWIZZLE : 1;
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unsigned int SWIZZLE_ENABLE : 1;
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#elif defined(BIGENDIAN_CPU)
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unsigned int SWIZZLE_ENABLE : 1;
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unsigned int CACHE_SWIZZLE : 1;
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unsigned int STRIDE : 14;
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unsigned int BASE_ADDRESS_HI : 16;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union SQ_BUF_RSRC_WORD1_GFX11 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int BASE_ADDRESS_HI : 16;
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unsigned int STRIDE : 14;
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unsigned int SWIZZLE_ENABLE : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int SWIZZLE_ENABLE : 2;
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unsigned int STRIDE : 14;
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unsigned int BASE_ADDRESS_HI : 16;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union SQ_BUF_RSRC_WORD2 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int NUM_RECORDS : 32;
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#elif defined(BIGENDIAN_CPU)
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unsigned int NUM_RECORDS : 32;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union SQ_BUF_RSRC_WORD3 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int DST_SEL_X : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_W : 3;
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unsigned int NUM_FORMAT : 3;
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unsigned int DATA_FORMAT : 4;
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unsigned int ELEMENT_SIZE : 2;
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unsigned int INDEX_STRIDE : 2;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int ATC__CI__VI : 1;
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unsigned int HASH_ENABLE : 1;
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unsigned int HEAP : 1;
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unsigned int MTYPE__CI__VI : 3;
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unsigned int TYPE : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int TYPE : 2;
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unsigned int MTYPE__CI__VI : 3;
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unsigned int HEAP : 1;
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unsigned int HASH_ENABLE : 1;
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unsigned int ATC__CI__VI : 1;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int INDEX_STRIDE : 2;
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unsigned int ELEMENT_SIZE : 2;
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unsigned int DATA_FORMAT : 4;
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unsigned int NUM_FORMAT : 3;
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unsigned int DST_SEL_W : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_X : 3;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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union SQ_BUF_RSRC_WORD3_GFX10 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int DST_SEL_X : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_W : 3;
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unsigned int FORMAT : 7;
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unsigned int RESERVED1 : 2;
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unsigned int INDEX_STRIDE : 2;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int RESOURCE_LEVEL : 1;
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unsigned int RESERVED2 : 3;
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unsigned int OOB_SELECT : 2;
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unsigned int TYPE : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int TYPE : 2;
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unsigned int OOB_SELECT : 2;
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unsigned int RESERVED2 : 3;
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unsigned int RESOURCE_LEVEL : 1;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int INDEX_STRIDE : 2;
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unsigned int RESERVED1 : 2;
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unsigned int FORMAT : 7;
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unsigned int DST_SEL_W : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_X : 3;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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// From V# Table
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union SQ_BUF_RSRC_WORD3_GFX11 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int DST_SEL_X : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_W : 3;
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unsigned int FORMAT : 6;
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unsigned int RESERVED1 : 3;
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unsigned int INDEX_STRIDE : 2;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int RESERVED2 : 4;
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unsigned int OOB_SELECT : 2;
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unsigned int TYPE : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int TYPE : 2;
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unsigned int OOB_SELECT : 2;
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unsigned int RESERVED2 : 4;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int INDEX_STRIDE : 2;
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unsigned int RESERVED1 : 3;
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unsigned int FORMAT : 6;
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unsigned int DST_SEL_W : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_X : 3;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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// From V# Table
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union SQ_BUF_RSRC_WORD3_GFX12 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int DST_SEL_X : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_W : 3;
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unsigned int FORMAT : 6;
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unsigned int RESERVED1 : 3;
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unsigned int INDEX_STRIDE : 2;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int WRITE_COMPRESS_ENABLE : 1;
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unsigned int COMPRESSION_EN : 1;
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unsigned int COMPRESSION_ACCESS_MODE : 2;
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unsigned int OOB_SELECT : 2;
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unsigned int TYPE : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int TYPE : 2;
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unsigned int OOB_SELECT : 2;
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unsigned int COMPRESSION_ACCESS_MODE : 2;
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unsigned int COMPRESSION_EN : 1;
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unsigned int WRITE_COMPRESS_ENABLE : 1;
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unsigned int ADD_TID_ENABLE : 1;
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unsigned int INDEX_STRIDE : 2;
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unsigned int RESERVED1 : 3;
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unsigned int FORMAT : 6;
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unsigned int DST_SEL_W : 3;
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unsigned int DST_SEL_Z : 3;
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unsigned int DST_SEL_Y : 3;
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unsigned int DST_SEL_X : 3;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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#endif // header guard
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