German Andryeyev
5319163521
git-subtree-dir: projects/rocr-runtime/libhsakmt/include/impl git-subtree-mainline:55f7d39fa5git-subtree-split:c34ec1e52f
123 righe
3.4 KiB
C++
123 righe
3.4 KiB
C++
#ifndef _WSL_INC_THUNK_PROXY_H_
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#define _WSL_INC_THUNK_PROXY_H_
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#include <vector>
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namespace thunk_proxy {
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enum AllocDomain {
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kSystem,
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kLocal,
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kUserMemory,
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kUserQueue,
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kDomainCount,
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};
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enum MemFlag {
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kFineGrain = (1ULL << 0),
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kKernarg = (1ULL << 1),
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};
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enum EngineFlag {
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KCOMPUTE0 = (1ULL << 0),
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KDRMDMA = (1ULL << 1),
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KDRMDMA1 = (1ULL << 2),
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};
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enum SchedLevel {
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kLow = 0,
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kNormal = 1,
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kHigh = 2,
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};
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struct HwsInfo {
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union {
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struct {
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uint32_t gfxHwsEnabled : 1;
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uint32_t computeHwsEnabled : 1;
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uint32_t dmaHwsEnabled : 1;
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uint32_t dma1HwsEnabled : 1;
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uint32_t reserved : 28;
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} hwsMask;
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uint32_t osHwsEnableFlags;
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};
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uint64_t engineOrdinalMask; // Indicates which engines (by ordinal) support MES HWS
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};
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typedef struct {
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int major;
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int minor;
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int stepping;
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bool is_dgpu;
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char product_name[MAX_PATH];
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uint64_t uuid;
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uint32_t family;
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uint32_t device_id;
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uint32_t wavefront_size;
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uint32_t compute_unit_count;
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uint32_t max_engine_clock_mhz;
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uint32_t watch_points_num;
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uint32_t pci_bus_addr;
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uint32_t memory_bus_width;
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uint32_t max_memory_clock_mhz;
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uint64_t gpu_counter_frequency;
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uint32_t wave_per_cu;
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uint32_t simd_per_cu;
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uint32_t max_scratch_slots_per_cu;
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uint32_t num_shader_engine;
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uint32_t shader_array_per_shader_engine;
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uint32_t domain;
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uint32_t num_gws;
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uint32_t asic_revision;
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uint64_t local_visible_heap_size;
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uint64_t local_invisible_heap_size;
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uint64_t non_local_heap_size;
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uint64_t private_aperture_base;
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uint64_t private_aperture_size;
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uint64_t shared_aperture_base;
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uint64_t shared_aperture_size;
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uint32_t user_queue_size;
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uint32_t lds_size;
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uint32_t big_page_alignment_size;
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uint32_t hw_big_page_min_alignment_size;
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uint32_t hw_big_page_alignment_size;
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bool enable_big_page_alignment;
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uint32_t mec_fw_version;
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uint32_t sdma_fw_version;
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uint32_t l1_cache_size;
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uint32_t l2_cache_size;
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uint32_t l3_cache_size;
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uint32_t gl2_cacheline_size;
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uint32_t num_cp_queues;
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HwsInfo hwsInfo;
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std::vector<int> sdma_schedid;
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uint32_t compute_schedid;
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bool state_shadowing_by_cpfw;
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bool platform_atomic_support;
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void *adapter_info;
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uint32_t kmd_version;
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} DeviceInfo;
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int EngineOrdinal(int engine, DeviceInfo *device_info);
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bool GetHwsEnabled(int engine, DeviceInfo *device_info);
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bool ShouldDisableGpuTimeout(int engine, DeviceInfo *device_info);
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bool ParseAdapterInfo(D3DKMT_HANDLE adapter, DeviceInfo *device_info);
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bool QueryAdapterSupported(unsigned int device_id);
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uint32_t QueueEngine2EngineFlag(uint32_t queue_engine);
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void SetAllocationInfo(void *data, uint64_t size, AllocDomain domain,
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uint64_t addr, uint32_t mem_flags, uint32_t engine_flag, const DeviceInfo &device_info);
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void GetAllocPrivDataSize(int *priv_drv_data_size, int *priv_alloc_data_size);
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void FillinAllocPrivDrvData(void *drv_priv, int priv_alloc_data_size);
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int GetSubmitPrivDataSize();
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void FillinSubmitPrivData(void *priv_data, D3DKMT_HANDLE queue, uint64_t command_addr,
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uint64_t command_size, bool is_hw_queue);
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int GetHwQueuePrivDataSize();
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void FillinHwQueuePrivData(void *priv_data, bool FwManagedGfxState, SchedLevel level = kNormal);
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int GetContextPrivDataSize();
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void FillinContextPrivData(void *priv_data, bool FwManagedGfxState);
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int GetPowerOptPrivDataSize();
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void FillinPowerOptPrivData(void *priv_data, bool restore);
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}
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#endif
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