Yong Zhao
6df62c78b8
The code is a snapshot up to this commit around July 31 2018. commit b00fadff36a3 Author: xinhui pan <xinhui.pan@amd.com> Date: Mon Jul 30 09:53:03 2018 +0800 kfdtest: skip MMapLarge test on apu Change-Id: I40e9a5a18e5c8f075e5290bb80532f1a3f689058 Signed-off-by: Yong Zhao <yong.zhao@amd.com>
276 строки
8.1 KiB
C
276 строки
8.1 KiB
C
/*
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* Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __PM4_PKT_STRUCT_COMMON_H__
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#define __PM4_PKT_STRUCT_COMMON_H__
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#ifndef PM4_HEADER_DEFINED
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#define PM4_HEADER_DEFINED
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typedef union PM4_TYPE_3_HEADER
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{
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struct
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{
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unsigned int predicate : 1; ///< predicated version of packet when set
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unsigned int shaderType: 1; ///< 0: Graphics, 1: Compute Shader
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unsigned int reserved1 : 6; ///< reserved
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unsigned int opcode : 8; ///< IT opcode
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unsigned int count : 14;///< number of DWORDs - 1 in the information body.
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unsigned int type : 2; ///< packet identifier. It should be 3 for type 3 packets
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};
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unsigned int u32All;
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} PM4_TYPE_3_HEADER;
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#endif // PM4_HEADER_DEFINED
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//--------------------DISPATCH_DIRECT--------------------
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typedef struct _PM4_DISPATCH_DIRECT
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{
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union
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{
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PM4_TYPE_3_HEADER header; ///header
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unsigned int ordinal1;
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};
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unsigned int dim_x;
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unsigned int dim_y;
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unsigned int dim_z;
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unsigned int dispatch_initiator;
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} PM4DISPATCH_DIRECT, *PPM4DISPATCH_DIRECT;
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//--------------------INDIRECT_BUFFER--------------------
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enum INDIRECT_BUFFER_cache_policy_enum { cache_policy_indirect_buffer_LRU_0 = 0, cache_policy_indirect_buffer_STREAM_1 = 1, cache_policy_indirect_buffer_BYPASS_2 = 2 };
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//--------------------EVENT_WRITE--------------------
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enum EVENT_WRITE_event_index_enum { event_index_event_write_OTHER_0 = 0, event_index_event_write_ZPASS_DONE_1 = 1, event_index_event_write_SAMPLE_PIPELINESTAT_2 = 2, event_index_event_write_SAMPLE_STREAMOUTSTAT_3 = 3, event_index_event_write_CS_VS_PS_PARTIAL_FLUSH_4 = 4, event_index_event_write_RESERVED_EOP_5 = 5, event_index_event_write_RESERVED_EOS_6 = 6, event_index_event_write_CACHE_FLUSH_7 = 7 };
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typedef struct _PM4_EVENT_WRITE
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{
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union
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{
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PM4_TYPE_3_HEADER header; ///header
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unsigned int ordinal1;
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};
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union
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{
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struct
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{
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unsigned int event_type:6;
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unsigned int reserved1:2;
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EVENT_WRITE_event_index_enum event_index:4;
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unsigned int reserved2:20;
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} bitfields2;
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unsigned int ordinal2;
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};
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union
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{
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struct
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{
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unsigned int reserved3:3;
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unsigned int address_lo:29;
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} bitfields3;
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unsigned int ordinal3;
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};
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union
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{
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struct
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{
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unsigned int address_hi:16;
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unsigned int reserved4:16;
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} bitfields4;
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unsigned int ordinal4;
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};
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} PM4EVENT_WRITE, *PPM4EVENT_WRITE;
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//--------------------SET_SH_REG--------------------
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typedef struct _PM4_SET_SH_REG
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{
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union
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{
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PM4_TYPE_3_HEADER header; ///header
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unsigned int ordinal1;
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};
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union
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{
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struct
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{
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unsigned int reg_offset:16;
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unsigned int reserved1:16;
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} bitfields2;
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unsigned int ordinal2;
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};
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unsigned int reg_data[1]; //1..N of these fields
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} PM4SET_SH_REG, *PPM4SET_SH_REG;
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//--------------------ACQUIRE_MEM--------------------
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enum ACQUIRE_MEM_engine_enum { engine_acquire_mem_PFP_0 = 0, engine_acquire_mem_ME_1 = 1 };
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typedef struct _PM4_ACQUIRE_MEM
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{
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union
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{
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PM4_TYPE_3_HEADER header; ///header
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unsigned int ordinal1;
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};
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union
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{
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struct
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{
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unsigned int coher_cntl:31;
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ACQUIRE_MEM_engine_enum engine:1;
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} bitfields2;
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unsigned int ordinal2;
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};
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unsigned int coher_size;
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union
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{
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struct
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{
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unsigned int coher_size_hi:8;
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unsigned int reserved1:24;
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} bitfields3;
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unsigned int ordinal4;
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};
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unsigned int coher_base_lo;
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union
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{
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struct
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{
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unsigned int coher_base_hi:25;
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unsigned int reserved2:7;
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} bitfields4;
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unsigned int ordinal6;
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};
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union
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{
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struct
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{
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unsigned int poll_interval:16;
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unsigned int reserved3:16;
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} bitfields5;
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unsigned int ordinal7;
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};
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} PM4ACQUIRE_MEM, *PPM4ACQUIRE_MEM;
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//--------------------MEC_INDIRECT_BUFFER--------------------
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typedef struct _PM4_MEC_INDIRECT_BUFFER
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{
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union
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{
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PM4_TYPE_3_HEADER header; ///header
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unsigned int ordinal1;
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};
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union
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{
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struct
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{
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unsigned int swap_function:2;
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unsigned int ib_base_lo:30;
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} bitfields2;
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unsigned int ordinal2;
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};
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union
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{
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struct
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{
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unsigned int ib_base_hi:16;
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unsigned int reserved1:16;
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} bitfields3;
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unsigned int ordinal3;
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};
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union
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{
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struct
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{
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unsigned int ib_size:20;
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unsigned int chain:1;
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unsigned int offload_polling:1;
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unsigned int volatile_setting:1;
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unsigned int valid:1;
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unsigned int vmid:4;
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INDIRECT_BUFFER_cache_policy_enum cache_policy:2;
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unsigned int reserved4:2;
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} bitfields4;
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unsigned int ordinal4;
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};
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} PM4MEC_INDIRECT_BUFFER, *PPM4MEC_INDIRECT_BUFFER;
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//--------------------MEC_WRITE_DATA--------------------
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enum MEC_WRITE_DATA_dst_sel_enum { dst_sel_mec_write_data_MEM_MAPPED_REGISTER_0 = 0, dst_sel_mec_write_data_TC_L2_2 = 2, dst_sel_mec_write_data_GDS_3 = 3, dst_sel_mec_write_data_MEMORY_5 = 5 };
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enum MEC_WRITE_DATA_addr_incr_enum { addr_incr_mec_write_data_INCREMENT_ADDR_0 = 0, addr_incr_mec_write_data_DO_NOT_INCREMENT_ADDR_1 = 1 };
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enum MEC_WRITE_DATA_wr_confirm_enum { wr_confirm_mec_write_data_DO_NOT_WAIT_FOR_CONFIRMATION_0 = 0, wr_confirm_mec_write_data_WAIT_FOR_CONFIRMATION_1 = 1 };
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enum MEC_WRITE_DATA_cache_policy_enum { cache_policy_mec_write_data_LRU_0 = 0, cache_policy_mec_write_data_STREAM_1 = 1, cache_policy_mec_write_data_BYPASS_2 = 2 };
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//--------------------MEC_RELEASE_MEM--------------------
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enum MEC_RELEASE_MEM_event_index_enum { event_index_mec_release_mem_EVENT_WRITE_EOP_5 = 5, event_index_mec_release_mem_CS_Done_6 = 6 };
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enum MEC_RELEASE_MEM_cache_policy_enum { cache_policy_mec_release_mem_LRU_0 = 0, cache_policy_mec_release_mem_STREAM_1 = 1, cache_policy_mec_release_mem_BYPASS_2 = 2 };
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enum MEC_RELEASE_MEM_dst_sel_enum { dst_sel_mec_release_mem_MEMORY_CONTROLLER_0 = 0, dst_sel_mec_release_mem_TC_L2_1 = 1 };
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enum MEC_RELEASE_MEM_int_sel_enum { int_sel_mec_release_mem_NONE_0 = 0, int_sel_mec_release_mem_SEND_INTERRUPT_ONLY_1 = 1, int_sel_mec_release_mem_SEND_INTERRUPT_AFTER_WRITE_CONFIRM_2 = 2, int_sel_mec_release_mem_SEND_DATA_AFTER_WRITE_CONFIRM_3 = 3 };
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enum MEC_RELEASE_MEM_data_sel_enum { data_sel_mec_release_mem_NONE_0 = 0, data_sel_mec_release_mem_SEND_32_BIT_LOW_1 = 1, data_sel_mec_release_mem_SEND_64_BIT_DATA_2 = 2, data_sel_mec_release_mem_SEND_GPU_CLOCK_COUNTER_3 = 3, data_sel_mec_release_mem_SEND_CP_PERFCOUNTER_HI_LO_4 = 4, data_sel_mec_release_mem_STORE_GDS_DATA_TO_MEMORY_5 = 5 };
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#endif
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