vedithal-amd
f9aa7be97c
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
1.4 KiB
1.4 KiB
| 1 | Dispatch_ID | GPU_ID | Queue_ID | PID | TID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Start_Timestamp | End_Timestamp | Correlation_ID | Kernel_ID | CPC_CPC_TCIU_BUSY | CPC_ME1_DC0_SPI_BUSY | SPI_RA_REQ_NO_ALLOC_CSN | SPI_VWC0_VDATA_VALID_WR | SQC_DCACHE_ATOMIC | SQC_DCACHE_MISSES | SQC_ICACHE_REQ | SQC_TC_STALL | SQ_INSTS_VALU_MUL_F16 | SQ_INST_LEVEL_LDS | SQ_WAVES_SAVED | TA_BUFFER_WRITE_WAVEFRONTS_sum | TA_TA_BUSY_sum | TCC_ATOMIC_sum | TCC_EA0_ATOMIC_LEVEL_sum | TCC_EA0_WRREQ_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_UTCL1_REQUEST_sum |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1 | 15744 | 15744 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248225042558134 | 1248225042580173 | 1 | 13 | 628.0 | 28511.0 | 18570.0 | 32768.0 | 0.0 | 72.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 730768.0 | 0.0 | 0.0 | 131072.0 | 0.0 | 0.0 | 0.0 | 128.0 | 524288.0 |
| 3 | 1 | 0 | 1 | 15744 | 15744 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248225043214988 | 1248225043231667 | 2 | 13 | 628.0 | 21899.0 | 17097.0 | 32768.0 | 0.0 | 72.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 587815.0 | 0.0 | 0.0 | 131072.0 | 0.0 | 0.0 | 0.0 | 128.0 | 524288.0 |
| 4 | 2 | 0 | 1 | 15744 | 15744 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248225043788046 | 1248225043804766 | 3 | 13 | 628.0 | 21865.0 | 17000.0 | 32768.0 | 0.0 | 72.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 587705.0 | 0.0 | 0.0 | 131072.0 | 0.0 | 0.0 | 0.0 | 128.0 | 524288.0 |