agunashe
85 строки
3.6 KiB
Makefile
85 строки
3.6 KiB
Makefile
# Copyright (c) 2020 - 2021 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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HIP_PATH?= $(wildcard /opt/rocm/hip)
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ifeq (,$(HIP_PATH))
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HIP_PATH=../../..
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endif
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HIPCC=$(HIP_PATH)/bin/hipcc
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CLANG=$(HIP_PATH)/../llvm/bin/clang
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LLVM_MC=$(HIP_PATH)/../llvm/bin/llvm-mc
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CLANG_OFFLOAD_BUNDLER=$(HIP_PATH)/../llvm/bin/clang-offload-bundler
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LLVM_AS=$(HIP_PATH)/../llvm/bin/llvm-as
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LLVM_DIS=$(HIP_PATH)/../llvm/bin/llvm-dis
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SRCS=square.cpp
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# Extracting the IR code, then creating an executable with the modified IR.
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SQ_HOST_BC=square_host.bc
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SQ_HOST_LL=square_host.ll
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SQ_HOST_OBJ=square_host.o
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SQ_DEVICE_OBJ=square_device.o
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SQ_DEVICE_HIPFB=offload_bundle.hipfb
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SQ_IR_EXE=square_ir.out
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MCIN_OBJ_GEN=hip_obj_gen.mcin
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GPU_ARCH1=gfx900
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GPU_ARCH2=gfx906
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.PHONY: test
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all: src_to_ir bc_to_ll ll_to_bc ir_to_exec
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src_to_ir:
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$(HIPCC) -c -emit-llvm --cuda-host-only -target x86_64-linux-gnu -o $(SQ_HOST_BC) $(SRCS)
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$(HIPCC) -c -emit-llvm --cuda-device-only --offload-arch=$(GPU_ARCH1) --offload-arch=$(GPU_ARCH2) $(SRCS)
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# By default, the LLVM IR Bitcode file names will be:
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# square-hip-amdgcn-amd-amdhsa-gfx900.bc
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# square-hip-amdgcn-amd-amdhsa-gfx906.bc
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bc_to_ll:
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$(LLVM_DIS) $(SQ_HOST_BC) -o $(SQ_HOST_LL)
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$(LLVM_DIS) square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH1).bc -o square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH1).ll
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$(LLVM_DIS) square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH2).bc -o square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH2).ll
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# You may modify the .ll LLVM IR files before the next step
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#
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# Note: hipcc does not work to convert .bc to .o, use clang instead.
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ll_to_bc:
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$(LLVM_AS) $(SQ_HOST_LL) -o $(SQ_HOST_BC)
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$(LLVM_AS) square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH1).ll -o square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH1).bc
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$(LLVM_AS) square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH2).ll -o square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH2).bc
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ir_to_exec:
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$(HIPCC) -c $(SQ_HOST_BC) -o $(SQ_HOST_OBJ)
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$(CLANG) -target amdgcn-amd-amdhsa -mcpu=$(GPU_ARCH1) square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH1).bc -o square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH1).o
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$(CLANG) -target amdgcn-amd-amdhsa -mcpu=$(GPU_ARCH2) square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH2).bc -o square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH2).o
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$(CLANG_OFFLOAD_BUNDLER) -type=o -bundle-align=4096 -targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa-$(GPU_ARCH1),hip-amdgcn-amd-amdhsa-$(GPU_ARCH2) -inputs=/dev/null,square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH1).o,square-hip-amdgcn-amd-amdhsa-$(GPU_ARCH2).o -outputs=$(SQ_DEVICE_HIPFB)
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$(LLVM_MC) $(MCIN_OBJ_GEN) -o $(SQ_DEVICE_OBJ) --filetype=obj
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$(HIPCC) $(SQ_HOST_OBJ) $(SQ_DEVICE_OBJ) -o $(SQ_IR_EXE)
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clean:
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rm -f *.o *.out *.hipfb *.s *.ll *.bc
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