Ding, Wei (xN/A) TX
41dc8c58e7
[git-p4: depot-paths = "//depot/stg/hsa/drivers/hsa/runtime/": change = 1125122]
98 lines
3.3 KiB
Plaintext
98 lines
3.3 KiB
Plaintext
version 0:20140528:$full:$large;
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extension "amd:gcn";
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extension "IMAGE";
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decl prog function &abort()();
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prog kernel &__OpenCL_bitonicSort_kernel(
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kernarg_u64 %__global_offset_0,
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kernarg_u64 %__global_offset_1,
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kernarg_u64 %__global_offset_2,
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kernarg_u64 %__printf_buffer,
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kernarg_u64 %__vqueue_pointer,
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kernarg_u64 %__aqlwrap_pointer,
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kernarg_u64 %theArray,
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kernarg_u32 %stage,
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kernarg_u32 %passOfStage,
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kernarg_u32 %direction)
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{
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pragma "AMD RTI", "ARGSTART:__OpenCL_bitonicSort_kernel";
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pragma "AMD RTI", "version:3:1:104";
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pragma "AMD RTI", "device:generic";
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pragma "AMD RTI", "uniqueid:1024";
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pragma "AMD RTI", "memory:private:0";
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pragma "AMD RTI", "memory:region:0";
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pragma "AMD RTI", "memory:local:0";
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pragma "AMD RTI", "value:__global_offset_0:u64:1:1:0";
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pragma "AMD RTI", "value:__global_offset_1:u64:1:1:16";
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pragma "AMD RTI", "value:__global_offset_2:u64:1:1:32";
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pragma "AMD RTI", "pointer:__printf_buffer:u8:1:1:48:uav:7:1:RW:0:0:0";
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pragma "AMD RTI", "value:__vqueue_pointer:u64:1:1:64";
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pragma "AMD RTI", "value:__aqlwrap_pointer:u64:1:1:80";
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pragma "AMD RTI", "pointer:theArray:u32:1:1:96:uav:7:4:RW:0:0:0";
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pragma "AMD RTI", "value:stage:u32:1:1:112";
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pragma "AMD RTI", "constarg:7:stage";
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pragma "AMD RTI", "value:passOfStage:u32:1:1:128";
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pragma "AMD RTI", "constarg:8:passOfStage";
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pragma "AMD RTI", "value:direction:u32:1:1:144";
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pragma "AMD RTI", "constarg:9:direction";
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pragma "AMD RTI", "function:1:0";
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pragma "AMD RTI", "memory:64bitABI";
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pragma "AMD RTI", "privateid:8";
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pragma "AMD RTI", "enqueue_kernel:0";
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pragma "AMD RTI", "kernel_index:0";
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pragma "AMD RTI", "reflection:0:size_t";
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pragma "AMD RTI", "reflection:1:size_t";
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pragma "AMD RTI", "reflection:2:size_t";
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pragma "AMD RTI", "reflection:3:size_t";
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pragma "AMD RTI", "reflection:4:size_t";
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pragma "AMD RTI", "reflection:5:size_t";
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pragma "AMD RTI", "reflection:6:uint*";
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pragma "AMD RTI", "reflection:7:uint";
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pragma "AMD RTI", "reflection:8:uint";
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pragma "AMD RTI", "reflection:9:uint";
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pragma "AMD RTI", "ARGEND:__OpenCL_bitonicSort_kernel";
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@__OpenCL_bitonicSort_kernel_entry:
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// BB#0: // %entry
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workitemabsid_u32 $s0, 0;
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cvt_u64_u32 $d0, $s0;
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ld_kernarg_align(8)_width(all)_u64 $d1, [%__global_offset_0];
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add_u64 $d0, $d0, $d1;
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cvt_u32_u64 $s1, $d0;
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ld_kernarg_align(4)_width(all)_u32 $s2, [%stage];
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shl_u32 $s0, 1, $s2;
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and_b32 $s0, $s1, $s0;
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ld_kernarg_align(4)_width(all)_u32 $s3, [%direction];
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sub_u32 $s4, 1, $s3;
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cmp_eq_b1_s32 $c0, $s0, 0;
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cmov_b32 $s0, $c0, $s3, $s4;
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ld_kernarg_align(4)_width(all)_u32 $s3, [%passOfStage];
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sub_u32 $s4, $s2, $s3;
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shl_u32 $s2, 1, $s4;
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add_u32 $s3, $s2, 4294967295;
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and_b32 $s3, $s1, $s3;
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shr_u32 $s1, $s1, $s4;
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mul_u32 $s1, $s2, $s1;
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shl_u32 $s1, $s1, 1;
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ld_kernarg_align(8)_width(all)_u64 $d1, [%theArray];
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add_u32 $s3, $s1, $s3;
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cvt_u64_u32 $d0, $s3;
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shl_u64 $d0, $d0, 2;
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add_u64 $d0, $d1, $d0;
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ld_global_align(4)_u32 $s1, [$d0];
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add_u32 $s2, $s3, $s2;
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cvt_u64_u32 $d2, $s2;
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shl_u64 $d2, $d2, 2;
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add_u64 $d1, $d1, $d2;
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ld_global_align(4)_u32 $s3, [$d1];
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max_u32 $s2, $s1, $s3;
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min_u32 $s1, $s1, $s3;
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cmp_eq_b1_s32 $c0, $s0, 0;
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cmov_b32 $s0, $c0, $s1, $s2;
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cmov_b32 $s1, $c0, $s2, $s1;
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st_global_align(4)_u32 $s1, [$d0];
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st_global_align(4)_u32 $s0, [$d1];
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ret;
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};
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