vedithal-amd
f9aa7be97c
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
8.8 KiB
8.8 KiB
| 1 | Dispatch_ID | GPU_ID | Queue_ID | PID | TID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Start_Timestamp | End_Timestamp | Correlation_ID | Kernel_ID | CPC_ME1_BUSY_FOR_PACKET_DECODE | CPC_SYNC_WRREQ_FIFO_BUSY | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_BUSY | GRBM_GUI_ACTIVE | SPI_CS0_WAVE | SPI_CS1_WAVE | SPI_CS2_WAVE | SPI_CS3_WAVE | SQC_DCACHE_HITS | SQC_ICACHE_MISSES | SQC_ICACHE_MISSES_DUPLICATE | SQ_IFETCH_LEVEL | SQ_INSTS_VALU_FMA_F64 | SQ_INSTS_VALU_MFMA_MOPS_I8 | SQ_VMEM_WR_TA_DATA_FIFO_FULL | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_FLAT_WAVEFRONTS_sum | TCC_EA0_RDREQ[0] | TCC_EA0_RDREQ[10] | TCC_EA0_RDREQ[11] | TCC_EA0_RDREQ[12] | TCC_EA0_RDREQ[13] | TCC_EA0_RDREQ[14] | TCC_EA0_RDREQ[15] | TCC_EA0_RDREQ[16] | TCC_EA0_RDREQ[17] | TCC_EA0_RDREQ[18] | TCC_EA0_RDREQ[19] | TCC_EA0_RDREQ[1] | TCC_EA0_RDREQ[20] | TCC_EA0_RDREQ[21] | TCC_EA0_RDREQ[22] | TCC_EA0_RDREQ[23] | TCC_EA0_RDREQ[25] | TCC_EA0_RDREQ[26] | TCC_EA0_RDREQ[27] | TCC_EA0_RDREQ[28] | TCC_EA0_RDREQ[29] | TCC_EA0_RDREQ[2] | TCC_EA0_RDREQ[30] | TCC_EA0_RDREQ[31] | TCC_EA0_RDREQ[32] | TCC_EA0_RDREQ[33] | TCC_EA0_RDREQ[34] | TCC_EA0_RDREQ[35] | TCC_EA0_RDREQ[36] | TCC_EA0_RDREQ[37] | TCC_EA0_RDREQ[38] | TCC_EA0_RDREQ[39] | TCC_EA0_RDREQ[3] | TCC_EA0_RDREQ[40] | TCC_EA0_RDREQ[41] | TCC_EA0_RDREQ[42] | TCC_EA0_RDREQ[43] | TCC_EA0_RDREQ[45] | TCC_EA0_RDREQ[46] | TCC_EA0_RDREQ[47] | TCC_EA0_RDREQ[48] | TCC_EA0_RDREQ[49] | TCC_EA0_RDREQ[50] | TCC_EA0_RDREQ[51] | TCC_EA0_RDREQ[52] | TCC_EA0_RDREQ[53] | TCC_EA0_RDREQ[54] | TCC_EA0_RDREQ[55] | TCC_EA0_RDREQ[56] | TCC_EA0_RDREQ[57] | TCC_EA0_RDREQ[58] | TCC_EA0_RDREQ[59] | TCC_EA0_RDREQ[5] | TCC_EA0_RDREQ[60] | TCC_EA0_RDREQ[61] | TCC_EA0_RDREQ[62] | TCC_EA0_RDREQ[63] | TCC_EA0_RDREQ[6] | TCC_EA0_RDREQ[7] | TCC_EA0_RDREQ[8] | TCC_EA0_RDREQ[9] | TCC_EA0_WRREQ_LEVEL[0] | TCC_EA0_WRREQ_LEVEL[10] | TCC_EA0_WRREQ_LEVEL[11] | TCC_EA0_WRREQ_LEVEL[12] | TCC_EA0_WRREQ_LEVEL[13] | TCC_EA0_WRREQ_LEVEL[14] | TCC_EA0_WRREQ_LEVEL[15] | TCC_EA0_WRREQ_LEVEL[16] | TCC_EA0_WRREQ_LEVEL[17] | TCC_EA0_WRREQ_LEVEL[18] | TCC_EA0_WRREQ_LEVEL[19] | TCC_EA0_WRREQ_LEVEL[1] | TCC_EA0_WRREQ_LEVEL[20] | TCC_EA0_WRREQ_LEVEL[21] | TCC_EA0_WRREQ_LEVEL[22] | TCC_EA0_WRREQ_LEVEL[23] | TCC_EA0_WRREQ_LEVEL[25] | TCC_EA0_WRREQ_LEVEL[26] | TCC_EA0_WRREQ_LEVEL[27] | TCC_EA0_WRREQ_LEVEL[28] | TCC_EA0_WRREQ_LEVEL[29] | TCC_EA0_WRREQ_LEVEL[2] | TCC_EA0_WRREQ_LEVEL[30] | TCC_EA0_WRREQ_LEVEL[31] | TCC_EA0_WRREQ_LEVEL[32] | TCC_EA0_WRREQ_LEVEL[33] | TCC_EA0_WRREQ_LEVEL[34] | TCC_EA0_WRREQ_LEVEL[35] | TCC_EA0_WRREQ_LEVEL[36] | TCC_EA0_WRREQ_LEVEL[37] | TCC_EA0_WRREQ_LEVEL[38] | TCC_EA0_WRREQ_LEVEL[39] | TCC_EA0_WRREQ_LEVEL[3] | TCC_EA0_WRREQ_LEVEL[40] | TCC_EA0_WRREQ_LEVEL[41] | TCC_EA0_WRREQ_LEVEL[42] | TCC_EA0_WRREQ_LEVEL[43] | TCC_EA0_WRREQ_LEVEL[45] | TCC_EA0_WRREQ_LEVEL[46] | TCC_EA0_WRREQ_LEVEL[47] | TCC_EA0_WRREQ_LEVEL[48] | TCC_EA0_WRREQ_LEVEL[49] | TCC_EA0_WRREQ_LEVEL[50] | TCC_EA0_WRREQ_LEVEL[51] | TCC_EA0_WRREQ_LEVEL[52] | TCC_EA0_WRREQ_LEVEL[53] | TCC_EA0_WRREQ_LEVEL[54] | TCC_EA0_WRREQ_LEVEL[55] | TCC_EA0_WRREQ_LEVEL[56] | TCC_EA0_WRREQ_LEVEL[57] | TCC_EA0_WRREQ_LEVEL[58] | TCC_EA0_WRREQ_LEVEL[59] | TCC_EA0_WRREQ_LEVEL[5] | TCC_EA0_WRREQ_LEVEL[60] | TCC_EA0_WRREQ_LEVEL[61] | TCC_EA0_WRREQ_LEVEL[62] | TCC_EA0_WRREQ_LEVEL[63] | TCC_EA0_WRREQ_LEVEL[6] | TCC_EA0_WRREQ_LEVEL[7] | TCC_EA0_WRREQ_LEVEL[8] | TCC_EA0_WRREQ_LEVEL[9] | TCC_NC_REQ_sum | TCC_REQ[0] | TCC_REQ[10] | TCC_REQ[11] | TCC_REQ[12] | TCC_REQ[13] | TCC_REQ[14] | TCC_REQ[15] | TCC_REQ[16] | TCC_REQ[17] | TCC_REQ[18] | TCC_REQ[19] | TCC_REQ[1] | TCC_REQ[20] | TCC_REQ[21] | TCC_REQ[22] | TCC_REQ[23] | TCC_REQ[25] | TCC_REQ[26] | TCC_REQ[27] | TCC_REQ[28] | TCC_REQ[29] | TCC_REQ[2] | TCC_REQ[30] | TCC_REQ[31] | TCC_REQ[32] | TCC_REQ[33] | TCC_REQ[34] | TCC_REQ[35] | TCC_REQ[36] | TCC_REQ[37] | TCC_REQ[38] | TCC_REQ[39] | TCC_REQ[3] | TCC_REQ[40] | TCC_REQ[41] | TCC_REQ[42] | TCC_REQ[43] | TCC_REQ[45] | TCC_REQ[46] | TCC_REQ[47] | TCC_REQ[48] | TCC_REQ[49] | TCC_REQ[50] | TCC_REQ[51] | TCC_REQ[52] | TCC_REQ[53] | TCC_REQ[54] | TCC_REQ[55] | TCC_REQ[56] | TCC_REQ[57] | TCC_REQ[58] | TCC_REQ[59] | TCC_REQ[5] | TCC_REQ[60] | TCC_REQ[61] | TCC_REQ[62] | TCC_REQ[63] | TCC_REQ[6] | TCC_REQ[7] | TCC_REQ[8] | TCC_REQ[9] | TCP_GATE_EN1_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_TOTAL_WRITE_sum | TD_ATOMIC_WAVEFRONT_sum | TD_TC_STALL_sum |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1 | 15737 | 15737 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248224501556303 | 1248224501579103 | 1 | 13 | 39762.0 | 8.0 | 3350.0 | 78383.0 | 78383.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 63304.0 | 72.0 | 1358.0 | 19849.0 | 0.0 | 0.0 | 0.0 | 73772.0 | 32768.0 | 2048.0 | 1029.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 2048.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1032.0 | 1025.0 | 1029.0 | 1024.0 | 2048.0 | 1024.0 | 1032.0 | 1029.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1029.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1032.0 | 1029.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1032.0 | 299809.0 | 150330.0 | 152966.0 | 140377.0 | 141618.0 | 143102.0 | 153709.0 | 289555.0 | 136667.0 | 135044.0 | 132763.0 | 136304.0 | 146473.0 | 146928.0 | 141940.0 | 138800.0 | 153648.0 | 153921.0 | 153401.0 | 142275.0 | 158958.0 | 137764.0 | 154480.0 | 160030.0 | 287362.0 | 150932.0 | 153809.0 | 136102.0 | 148758.0 | 146780.0 | 137156.0 | 142600.0 | 132260.0 | 153858.0 | 148372.0 | 158797.0 | 150948.0 | 156084.0 | 155637.0 | 155676.0 | 134811.0 | 154657.0 | 151789.0 | 152058.0 | 156935.0 | 147692.0 | 137836.0 | 152194.0 | 155650.0 | 149350.0 | 159350.0 | 155714.0 | 151894.0 | 143590.0 | 140617.0 | 158498.0 | 151931.0 | 149816.0 | 134354.0 | 152344.0 | 153376.0 | 0.0 | 6144.0 | 3145.0 | 3072.0 | 3072.0 | 3073.0 | 3145.0 | 3072.0 | 6144.0 | 3072.0 | 3073.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3145.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3114.0 | 3090.0 | 3145.0 | 3072.0 | 6144.0 | 3072.0 | 3114.0 | 3145.0 | 3072.0 | 3072.0 | 3073.0 | 3145.0 | 3145.0 | 3090.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3114.0 | 3145.0 | 3073.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3114.0 | 1418304.0 | 0.0 | 0.0 | 1048576.0 | 0.0 | 571910.0 |
| 3 | 1 | 0 | 1 | 15737 | 15737 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248224502357113 | 1248224502373752 | 2 | 13 | 35094.0 | 8.0 | 3391.0 | 64716.0 | 64716.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 63304.0 | 72.0 | 996.0 | 17914.0 | 0.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 2048.0 | 1028.0 | 1024.0 | 1025.0 | 1026.0 | 1028.0 | 1024.0 | 2049.0 | 1024.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1024.0 | 1028.0 | 1024.0 | 2048.0 | 1025.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1028.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1025.0 | 1026.0 | 1028.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1026.0 | 307368.0 | 162005.0 | 160446.0 | 151060.0 | 153141.0 | 157304.0 | 151470.0 | 305183.0 | 146408.0 | 156888.0 | 152592.0 | 146297.0 | 143934.0 | 145080.0 | 157918.0 | 159116.0 | 146547.0 | 154796.0 | 157202.0 | 148817.0 | 159205.0 | 153646.0 | 161241.0 | 155953.0 | 316781.0 | 151490.0 | 159946.0 | 158706.0 | 146499.0 | 145428.0 | 160731.0 | 157547.0 | 151609.0 | 154421.0 | 158188.0 | 161612.0 | 161330.0 | 158057.0 | 162267.0 | 154697.0 | 156653.0 | 151979.0 | 161987.0 | 154131.0 | 157525.0 | 139803.0 | 153051.0 | 159171.0 | 150842.0 | 160845.0 | 161000.0 | 157519.0 | 152887.0 | 158287.0 | 158280.0 | 149117.0 | 164042.0 | 142572.0 | 153599.0 | 158627.0 | 147290.0 | 0.0 | 6144.0 | 3144.0 | 3072.0 | 3073.0 | 3091.0 | 3144.0 | 3072.0 | 6145.0 | 3072.0 | 3091.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3108.0 | 3072.0 | 3144.0 | 3072.0 | 6144.0 | 3073.0 | 3108.0 | 3144.0 | 3072.0 | 3072.0 | 3091.0 | 3144.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3073.0 | 3108.0 | 3144.0 | 3091.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3108.0 | 1062800.0 | 0.0 | 0.0 | 1048576.0 | 0.0 | 347780.0 |
| 4 | 2 | 0 | 1 | 15737 | 15737 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248224503046887 | 1248224503063847 | 3 | 13 | 35834.0 | 8.0 | 376.0 | 62877.0 | 62877.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 63304.0 | 72.0 | 1039.0 | 18047.0 | 0.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 2048.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 2048.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1025.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1024.0 | 1028.0 | 1024.0 | 2048.0 | 1024.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1025.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1028.0 | 1026.0 | 297690.0 | 151572.0 | 166245.0 | 153966.0 | 152335.0 | 145177.0 | 155284.0 | 305526.0 | 157035.0 | 150029.0 | 149885.0 | 155828.0 | 160141.0 | 154195.0 | 151522.0 | 154137.0 | 145865.0 | 151468.0 | 159289.0 | 156374.0 | 151317.0 | 155030.0 | 151653.0 | 156309.0 | 306747.0 | 153464.0 | 147495.0 | 145937.0 | 158635.0 | 156119.0 | 151800.0 | 147953.0 | 147121.0 | 150499.0 | 157270.0 | 159094.0 | 162440.0 | 154810.0 | 149439.0 | 150285.0 | 151413.0 | 156221.0 | 151239.0 | 147915.0 | 162813.0 | 149282.0 | 153992.0 | 156456.0 | 151068.0 | 159130.0 | 163566.0 | 164073.0 | 155062.0 | 156829.0 | 142277.0 | 152961.0 | 146665.0 | 148927.0 | 154406.0 | 155546.0 | 152788.0 | 0.0 | 6144.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 6144.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3090.0 | 3144.0 | 3072.0 | 3072.0 | 3108.0 | 3072.0 | 3144.0 | 3072.0 | 6144.0 | 3072.0 | 3108.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3090.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3144.0 | 3072.0 | 3072.0 | 3108.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3144.0 | 3108.0 | 1074680.0 | 0.0 | 0.0 | 1048576.0 | 0.0 | 343195.0 |