vedithal-amd
f9aa7be97c
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
9.5 KiB
9.5 KiB
| 1 | Dispatch_ID | GPU_ID | Queue_ID | PID | TID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Start_Timestamp | End_Timestamp | Correlation_ID | Kernel_ID | CPC_CANE_STALL | CPC_CPC_STAT_STALL | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | GRBM_COUNT | GRBM_SPI_BUSY | SPI_CS0_CRAWLER_STALL | SPI_CS1_CRAWLER_STALL | SPI_CS2_CRAWLER_STALL | SPI_CS3_CRAWLER_STALL | SQ_ACTIVE_INST_VMEM | SQ_INSTS_GDS | SQ_INSTS_LDS_ATOMIC | SQ_INSTS_VALU_MFMA_F16 | SQ_INSTS_VALU_MFMA_MOPS_F32 | SQ_INSTS_VSKIPPED | SQ_INST_LEVEL_VMEM | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TCC_EA0_WRREQ[0] | TCC_EA0_WRREQ[10] | TCC_EA0_WRREQ[11] | TCC_EA0_WRREQ[12] | TCC_EA0_WRREQ[14] | TCC_EA0_WRREQ[15] | TCC_EA0_WRREQ[16] | TCC_EA0_WRREQ[17] | TCC_EA0_WRREQ[18] | TCC_EA0_WRREQ[19] | TCC_EA0_WRREQ[1] | TCC_EA0_WRREQ[21] | TCC_EA0_WRREQ[22] | TCC_EA0_WRREQ[23] | TCC_EA0_WRREQ[24] | TCC_EA0_WRREQ[25] | TCC_EA0_WRREQ[26] | TCC_EA0_WRREQ[27] | TCC_EA0_WRREQ[28] | TCC_EA0_WRREQ[2] | TCC_EA0_WRREQ[30] | TCC_EA0_WRREQ[31] | TCC_EA0_WRREQ[32] | TCC_EA0_WRREQ[33] | TCC_EA0_WRREQ[34] | TCC_EA0_WRREQ[35] | TCC_EA0_WRREQ[36] | TCC_EA0_WRREQ[37] | TCC_EA0_WRREQ[38] | TCC_EA0_WRREQ[39] | TCC_EA0_WRREQ[3] | TCC_EA0_WRREQ[41] | TCC_EA0_WRREQ[42] | TCC_EA0_WRREQ[43] | TCC_EA0_WRREQ[44] | TCC_EA0_WRREQ[45] | TCC_EA0_WRREQ[46] | TCC_EA0_WRREQ[47] | TCC_EA0_WRREQ[48] | TCC_EA0_WRREQ[49] | TCC_EA0_WRREQ[50] | TCC_EA0_WRREQ[51] | TCC_EA0_WRREQ[52] | TCC_EA0_WRREQ[53] | TCC_EA0_WRREQ[54] | TCC_EA0_WRREQ[55] | TCC_EA0_WRREQ[57] | TCC_EA0_WRREQ[58] | TCC_EA0_WRREQ[59] | TCC_EA0_WRREQ[5] | TCC_EA0_WRREQ[60] | TCC_EA0_WRREQ[61] | TCC_EA0_WRREQ[62] | TCC_EA0_WRREQ[63] | TCC_EA0_WRREQ[6] | TCC_EA0_WRREQ[7] | TCC_EA0_WRREQ[8] | TCC_EA0_WRREQ[9] | TCC_MISS[0] | TCC_MISS[10] | TCC_MISS[11] | TCC_MISS[12] | TCC_MISS[14] | TCC_MISS[15] | TCC_MISS[16] | TCC_MISS[17] | TCC_MISS[18] | TCC_MISS[19] | TCC_MISS[1] | TCC_MISS[21] | TCC_MISS[22] | TCC_MISS[23] | TCC_MISS[24] | TCC_MISS[25] | TCC_MISS[26] | TCC_MISS[27] | TCC_MISS[28] | TCC_MISS[2] | TCC_MISS[30] | TCC_MISS[31] | TCC_MISS[32] | TCC_MISS[33] | TCC_MISS[34] | TCC_MISS[35] | TCC_MISS[36] | TCC_MISS[37] | TCC_MISS[38] | TCC_MISS[39] | TCC_MISS[3] | TCC_MISS[41] | TCC_MISS[42] | TCC_MISS[43] | TCC_MISS[44] | TCC_MISS[45] | TCC_MISS[46] | TCC_MISS[47] | TCC_MISS[48] | TCC_MISS[49] | TCC_MISS[50] | TCC_MISS[51] | TCC_MISS[52] | TCC_MISS[53] | TCC_MISS[54] | TCC_MISS[55] | TCC_MISS[57] | TCC_MISS[58] | TCC_MISS[59] | TCC_MISS[5] | TCC_MISS[60] | TCC_MISS[61] | TCC_MISS[62] | TCC_MISS[63] | TCC_MISS[6] | TCC_MISS[7] | TCC_MISS[8] | TCC_MISS[9] | TCC_READ[0] | TCC_READ[10] | TCC_READ[11] | TCC_READ[12] | TCC_READ[14] | TCC_READ[15] | TCC_READ[16] | TCC_READ[17] | TCC_READ[18] | TCC_READ[19] | TCC_READ[1] | TCC_READ[21] | TCC_READ[22] | TCC_READ[23] | TCC_READ[24] | TCC_READ[25] | TCC_READ[26] | TCC_READ[27] | TCC_READ[28] | TCC_READ[2] | TCC_READ[30] | TCC_READ[31] | TCC_READ[32] | TCC_READ[33] | TCC_READ[34] | TCC_READ[35] | TCC_READ[36] | TCC_READ[37] | TCC_READ[38] | TCC_READ[39] | TCC_READ[3] | TCC_READ[41] | TCC_READ[42] | TCC_READ[43] | TCC_READ[44] | TCC_READ[45] | TCC_READ[46] | TCC_READ[47] | TCC_READ[48] | TCC_READ[49] | TCC_READ[50] | TCC_READ[51] | TCC_READ[52] | TCC_READ[53] | TCC_READ[54] | TCC_READ[55] | TCC_READ[57] | TCC_READ[58] | TCC_READ[59] | TCC_READ[5] | TCC_READ[60] | TCC_READ[61] | TCC_READ[62] | TCC_READ[63] | TCC_READ[6] | TCC_READ[7] | TCC_READ[8] | TCC_READ[9] | TCC_WRITE[0] | TCC_WRITE[10] | TCC_WRITE[11] | TCC_WRITE[12] | TCC_WRITE[14] | TCC_WRITE[15] | TCC_WRITE[16] | TCC_WRITE[17] | TCC_WRITE[18] | TCC_WRITE[19] | TCC_WRITE[1] | TCC_WRITE[21] | TCC_WRITE[22] | TCC_WRITE[23] | TCC_WRITE[24] | TCC_WRITE[25] | TCC_WRITE[26] | TCC_WRITE[27] | TCC_WRITE[28] | TCC_WRITE[2] | TCC_WRITE[30] | TCC_WRITE[31] | TCC_WRITE[32] | TCC_WRITE[33] | TCC_WRITE[34] | TCC_WRITE[35] | TCC_WRITE[36] | TCC_WRITE[37] | TCC_WRITE[38] | TCC_WRITE[39] | TCC_WRITE[3] | TCC_WRITE[41] | TCC_WRITE[42] | TCC_WRITE[43] | TCC_WRITE[44] | TCC_WRITE[45] | TCC_WRITE[46] | TCC_WRITE[47] | TCC_WRITE[48] | TCC_WRITE[49] | TCC_WRITE[50] | TCC_WRITE[51] | TCC_WRITE[52] | TCC_WRITE[53] | TCC_WRITE[54] | TCC_WRITE[55] | TCC_WRITE[57] | TCC_WRITE[58] | TCC_WRITE[59] | TCC_WRITE[5] | TCC_WRITE[60] | TCC_WRITE[61] | TCC_WRITE[62] | TCC_WRITE[63] | TCC_WRITE[6] | TCC_WRITE[7] | TCC_WRITE[8] | TCC_WRITE[9] | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_RW_READ_REQ_sum | TCP_TCP_LATENCY_sum | TD_COALESCABLE_WAVEFRONT_sum | TD_SPI_STALL_sum |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1 | 15758 | 15758 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248226140812256 | 1248226140833735 | 1 | 13 | 0.0 | 16354.0 | 2108.0 | 0.0 | 74761.0 | 37009.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 256862.0 | 0.0 | 0.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4098.0 | 2048.0 | 2048.0 | 2052.0 | 2050.0 | 2049.0 | 4097.0 | 4096.0 | 2050.0 | 2048.0 | 4098.0 | 2048.0 | 2048.0 | 2051.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2052.0 | 2048.0 | 4102.0 | 2048.0 | 2050.0 | 2049.0 | 2048.0 | 2051.0 | 2050.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2051.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2052.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2050.0 | 1024.0 | 1024.0 | 1028.0 | 1096.0 | 1060.0 | 2066.0 | 2048.0 | 1096.0 | 1024.0 | 2050.0 | 1024.0 | 1024.0 | 1097.0 | 1024.0 | 1096.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1098.0 | 1024.0 | 2054.0 | 1024.0 | 1096.0 | 1060.0 | 1024.0 | 1027.0 | 1096.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1026.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 2048.0 | 1024.0 | 1097.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1098.0 | 1024.0 | 1024.0 | 1026.0 | 1024.0 | 1096.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1060.0 | 1096.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 0.0 | 0.0 | 65536.0 | 12901602.0 | 0.0 | 601.0 |
| 3 | 1 | 0 | 1 | 15758 | 15758 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248226141632504 | 1248226141649503 | 2 | 13 | 0.0 | 14445.0 | 2112.0 | 0.0 | 66766.0 | 29059.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 186838.0 | 0.0 | 0.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4098.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2049.0 | 4097.0 | 4096.0 | 2050.0 | 2048.0 | 4096.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2050.0 | 2048.0 | 4097.0 | 2048.0 | 2050.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 4097.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2067.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1060.0 | 2049.0 | 2048.0 | 1096.0 | 1024.0 | 2048.0 | 1025.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1096.0 | 1024.0 | 2049.0 | 1024.0 | 1096.0 | 1060.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1025.0 | 1024.0 | 1096.0 | 1024.0 | 1042.0 | 2049.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1025.0 | 1025.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1096.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 0.0 | 0.0 | 65536.0 | 8973198.0 | 0.0 | 897.0 |
| 4 | 2 | 0 | 1 | 15758 | 15758 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248226142354637 | 1248226142371716 | 3 | 13 | 0.0 | 11292.0 | 2055.0 | 0.0 | 63585.0 | 29133.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 186316.0 | 0.0 | 0.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4097.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 4096.0 | 4096.0 | 2050.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2050.0 | 2048.0 | 4097.0 | 2048.0 | 2050.0 | 2049.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2066.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 2048.0 | 2048.0 | 1096.0 | 1024.0 | 2048.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1096.0 | 1024.0 | 2066.0 | 1024.0 | 1096.0 | 1060.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 2048.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1096.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 0.0 | 0.0 | 65536.0 | 8951646.0 | 0.0 | 876.0 |