vedithal-amd
f9aa7be97c
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
1.4 KiB
1.4 KiB
| 1 | Dispatch_ID | GPU_ID | Queue_ID | PID | TID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Start_Timestamp | End_Timestamp | Correlation_ID | Kernel_ID | CPC_CANE_BUSY | CPC_GD_BUSY | SPI_RA_REQ_NO_ALLOC | SPI_SWC_CSC_WR | SQC_DCACHE_REQ_READ_4 | SQC_TC_DATA_READ_REQ | SQ_INSTS_VALU_INT64 | SQ_INSTS_VALU_MFMA_MOPS_F16 | SQ_INSTS_VALU_MFMA_MOPS_F6F4 | SQ_INSTS_VALU_TRANS_F64 | SQ_INSTS_VMEM | SQ_VALU_MFMA_BUSY_CYCLES | TA_BUFFER_READ_WAVEFRONTS_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TCC_CC_REQ_sum | TCC_EA0_RDREQ_LEVEL_sum | TCC_EA0_RD_UNCACHED_32B_sum | TCC_RW_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | TCP_TCC_NC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TCP_UTCL1_PERMISSION_MISS_sum |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1 | 15779 | 15779 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248227786612853 | 1248227786635252 | 1 | 13 | 630.0 | 30469.0 | 12744.0 | 32768.0 | 0.0 | 72.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 22666001.0 | 58.0 | 197976.0 | 406733.0 | 0.0 | 0.0 | 0.0 |
| 3 | 1 | 0 | 1 | 15779 | 15779 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248227787316865 | 1248227787333785 | 2 | 13 | 631.0 | 22019.0 | 4288.0 | 32768.0 | 0.0 | 72.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 11922030.0 | 16.0 | 197976.0 | 289225.0 | 0.0 | 0.0 | 0.0 |
| 4 | 2 | 0 | 1 | 15779 | 15779 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1248227787897083 | 1248227787913762 | 3 | 13 | 630.0 | 21586.0 | 3860.0 | 32768.0 | 0.0 | 72.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 11792534.0 | 0.0 | 197976.0 | 286818.0 | 0.0 | 0.0 | 0.0 |