rocm-systems/tests/workloads/dispatch_0_1/MI200/pmc_perf.csv

1	Dispatch_ID	Kernel_Name	GPU_ID	Grid_Size	Workgroup_Size	LDS_Per_Workgroup	Scratch_Per_Workitem	Arch_VGPR	Accum_VGPR	SGPR	wave_size	obj	SQ_INSTS_VSKIPPED	SQ_INSTS	SQ_INSTS_VALU	SQ_INSTS_VALU_ADD_F16	SQ_INSTS_VALU_MUL_F16	SQ_INSTS_VALU_FMA_F16	SQ_INSTS_VALU_TRANS_F16	SQ_INSTS_VALU_ADD_F32	GRBM_SPI_BUSY	TCP_READ_TAGCONFLICT_STALL_CYCLES_sum	TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum	TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum	TCP_TA_TCP_STATE_READ_sum	TA_BUFFER_READ_WAVEFRONTS_sum	TA_BUFFER_WRITE_WAVEFRONTS_sum	TD_SPI_STALL_sum	TD_LOAD_WAVEFRONT_sum	SPI_CSN_NUM_THREADGROUPS	SPI_CSN_WAVE	CPC_CPC_TCIU_BUSY	CPC_CPC_TCIU_IDLE	CPF_CPF_TCIU_BUSY	CPF_CPF_TCIU_STALL	TCC_NC_REQ_sum	TCC_UC_REQ_sum	TCC_CC_REQ_sum	TCC_RW_REQ_sum	wave_size_1	obj_1	SQ_ACTIVE_INST_SCA	SQ_ACTIVE_INST_EXP_GDS	SQ_ACTIVE_INST_MISC	SQ_ACTIVE_INST_FLAT	SQ_INST_CYCLES_VMEM_WR	SQ_INST_CYCLES_VMEM_RD	SQ_INST_CYCLES_SMEM	SQ_INST_CYCLES_SALU	TCP_TCP_LATENCY_sum	TCP_TCC_READ_REQ_LATENCY_sum	TCP_TCC_WRITE_REQ_LATENCY_sum	TCP_TCC_READ_REQ_sum	TA_ADDR_STALLED_BY_TD_CYCLES_sum	TA_DATA_STALLED_BY_TC_CYCLES_sum	SPI_RA_SGPR_SIMD_FULL_CSN	SPI_RA_LDS_CU_FULL_CSN	CPC_ME1_DC0_SPI_BUSY	TCC_EA_WRREQ_STALL_sum	TCC_EA_RDREQ_sum	TCC_EA_RDREQ_32B_sum	TCC_EA_RD_UNCACHED_32B_sum	wave_size_2	obj_2	SQC_ICACHE_MISSES_DUPLICATE	SQC_DCACHE_INPUT_VALID_READYB	SQC_DCACHE_ATOMIC	SQC_DCACHE_REQ_READ_8	SQC_DCACHE_REQ	SQC_DCACHE_HITS	SQC_DCACHE_MISSES	SQC_DCACHE_MISSES_DUPLICATE	wave_size_3	obj_3	SQC_TC_DATA_WRITE_REQ	SQC_TC_DATA_ATOMIC_REQ	SQC_TC_STALL	SQC_TC_REQ	SQC_DCACHE_REQ_READ_16	SQC_ICACHE_REQ	SQC_ICACHE_HITS	SQC_ICACHE_MISSES	wave_size_4	obj_4	TCC_ATOMIC[0]	TCC_CYCLE[0]	TCC_EA_ATOMIC[0]	TCC_EA_ATOMIC_LEVEL[0]	TCC_ATOMIC[1]	TCC_CYCLE[1]	TCC_EA_ATOMIC[1]	TCC_EA_ATOMIC_LEVEL[1]	TCC_ATOMIC[2]	TCC_CYCLE[2]	TCC_EA_ATOMIC[2]	TCC_EA_ATOMIC_LEVEL[2]	TCC_ATOMIC[3]	TCC_CYCLE[3]	TCC_EA_ATOMIC[3]	TCC_EA_ATOMIC_LEVEL[3]	TCC_ATOMIC[4]	TCC_CYCLE[4]	TCC_EA_ATOMIC[4]	TCC_EA_ATOMIC_LEVEL[4]	TCC_ATOMIC[5]	TCC_CYCLE[5]	TCC_EA_ATOMIC[5]	TCC_EA_ATOMIC_LEVEL[5]	TCC_ATOMIC[6]	TCC_CYCLE[6]	TCC_EA_ATOMIC[6]	TCC_EA_ATOMIC_LEVEL[6]	TCC_ATOMIC[7]	TCC_CYCLE[7]	TCC_EA_ATOMIC[7]	TCC_EA_ATOMIC_LEVEL[7]	TCC_ATOMIC[8]	TCC_CYCLE[8]	TCC_EA_ATOMIC[8]	TCC_EA_ATOMIC_LEVEL[8]	TCC_ATOMIC[9]	TCC_CYCLE[9]	TCC_EA_ATOMIC[9]	TCC_EA_ATOMIC_LEVEL[9]	TCC_ATOMIC[10]	TCC_CYCLE[10]	TCC_EA_ATOMIC[10]	TCC_EA_ATOMIC_LEVEL[10]	TCC_ATOMIC[11]	TCC_CYCLE[11]	TCC_EA_ATOMIC[11]	TCC_EA_ATOMIC_LEVEL[11]	TCC_ATOMIC[12]	TCC_CYCLE[12]	TCC_EA_ATOMIC[12]	TCC_EA_ATOMIC_LEVEL[12]	TCC_ATOMIC[13]	TCC_CYCLE[13]	TCC_EA_ATOMIC[13]	TCC_EA_ATOMIC_LEVEL[13]	TCC_ATOMIC[14]	TCC_CYCLE[14]	TCC_EA_ATOMIC[14]	TCC_EA_ATOMIC_LEVEL[14]	TCC_ATOMIC[15]	TCC_CYCLE[15]	TCC_EA_ATOMIC[15]	TCC_EA_ATOMIC_LEVEL[15]	TCC_ATOMIC[16]	TCC_CYCLE[16]	TCC_EA_ATOMIC[16]	TCC_EA_ATOMIC_LEVEL[16]	TCC_ATOMIC[17]	TCC_CYCLE[17]	TCC_EA_ATOMIC[17]	TCC_EA_ATOMIC_LEVEL[17]	TCC_ATOMIC[18]	TCC_CYCLE[18]	TCC_EA_ATOMIC[18]	TCC_EA_ATOMIC_LEVEL[18]	TCC_ATOMIC[19]	TCC_CYCLE[19]	TCC_EA_ATOMIC[19]	TCC_EA_ATOMIC_LEVEL[19]	TCC_ATOMIC[20]	TCC_CYCLE[20]	TCC_EA_ATOMIC[20]	TCC_EA_ATOMIC_LEVEL[20]	TCC_ATOMIC[21]	TCC_CYCLE[21]	TCC_EA_ATOMIC[21]	TCC_EA_ATOMIC_LEVEL[21]	TCC_ATOMIC[22]	TCC_CYCLE[22]	TCC_EA_ATOMIC[22]	TCC_EA_ATOMIC_LEVEL[22]	TCC_ATOMIC[23]	TCC_CYCLE[23]	TCC_EA_ATOMIC[23]	TCC_EA_ATOMIC_LEVEL[23]	TCC_ATOMIC[24]	TCC_CYCLE[24]	TCC_EA_ATOMIC[24]	TCC_EA_ATOMIC_LEVEL[24]	TCC_ATOMIC[25]	TCC_CYCLE[25]	TCC_EA_ATOMIC[25]	TCC_EA_ATOMIC_LEVEL[25]	TCC_ATOMIC[26]	TCC_CYCLE[26]	TCC_EA_ATOMIC[26]	TCC_EA_ATOMIC_LEVEL[26]	TCC_ATOMIC[27]	TCC_CYCLE[27]	TCC_EA_ATOMIC[27]	TCC_EA_ATOMIC_LEVEL[27]	TCC_ATOMIC[28]	TCC_CYCLE[28]	TCC_EA_ATOMIC[28]	TCC_EA_ATOMIC_LEVEL[28]	TCC_ATOMIC[29]	TCC_CYCLE[29]	TCC_EA_ATOMIC[29]	TCC_EA_ATOMIC_LEVEL[29]	TCC_ATOMIC[30]	TCC_CYCLE[30]	TCC_EA_ATOMIC[30]	TCC_EA_ATOMIC_LEVEL[30]	TCC_ATOMIC[31]	TCC_CYCLE[31]	TCC_EA_ATOMIC[31]	TCC_EA_ATOMIC_LEVEL[31]	wave_size_5	obj_5	TCC_RW_REQ[0]	TCC_TOO_MANY_EA_WRREQS_STALL[0]	TCC_WRITE[0]	TCC_RW_REQ[1]	TCC_TOO_MANY_EA_WRREQS_STALL[1]	TCC_WRITE[1]	TCC_RW_REQ[2]	TCC_TOO_MANY_EA_WRREQS_STALL[2]	TCC_WRITE[2]	TCC_RW_REQ[3]	TCC_TOO_MANY_EA_WRREQS_STALL[3]	TCC_WRITE[3]	TCC_RW_REQ[4]	TCC_TOO_MANY_EA_WRREQS_STALL[4]	TCC_WRITE[4]	TCC_RW_REQ[5]	TCC_TOO_MANY_EA_WRREQS_STALL[5]	TCC_WRITE[5]	TCC_RW_REQ[6]	TCC_TOO_MANY_EA_WRREQS_STALL[6]	TCC_WRITE[6]	TCC_RW_REQ[7]	TCC_TOO_MANY_EA_WRREQS_STALL[7]	TCC_WRITE[7]	TCC_RW_REQ[8]	TCC_TOO_MANY_EA_WRREQS_STALL[8]	TCC_WRITE[8]	TCC_RW_REQ[9]	TCC_TOO_MANY_EA_WRREQS_STALL[9]	TCC_WRITE[9]	TCC_RW_REQ[10]	TCC_TOO_MANY_EA_WRREQS_STALL[10]	TCC_WRITE[10]	TCC_RW_REQ[11]	TCC_TOO_MANY_EA_WRREQS_STALL[11]	TCC_WRITE[11]	TCC_RW_REQ[12]	TCC_TOO_MANY_EA_WRREQS_STALL[12]	TCC_WRITE[12]	TCC_RW_REQ[13]	TCC_TOO_MANY_EA_WRREQS_STALL[13]	TCC_WRITE[13]	TCC_RW_REQ[14]	TCC_TOO_MANY_EA_WRREQS_STALL[14]	TCC_WRITE[14]	TCC_RW_REQ[15]	TCC_TOO_MANY_EA_WRREQS_STALL[15]	TCC_WRITE[15]	TCC_RW_REQ[16]	TCC_TOO_MANY_EA_WRREQS_STALL[16]	TCC_WRITE[16]	TCC_RW_REQ[17]	TCC_TOO_MANY_EA_WRREQS_STALL[17]	TCC_WRITE[17]	TCC_RW_REQ[18]	TCC_TOO_MANY_EA_WRREQS_STALL[18]	TCC_WRITE[18]	TCC_RW_REQ[19]	TCC_TOO_MANY_EA_WRREQS_STALL[19]	TCC_WRITE[19]	TCC_RW_REQ[20]	TCC_TOO_MANY_EA_WRREQS_STALL[20]	TCC_WRITE[20]	TCC_RW_REQ[21]	TCC_TOO_MANY_EA_WRREQS_STALL[21]	TCC_WRITE[21]	TCC_RW_REQ[22]	TCC_TOO_MANY_EA_WRREQS_STALL[22]	TCC_WRITE[22]	TCC_RW_REQ[23]	TCC_TOO_MANY_EA_WRREQS_STALL[23]	TCC_WRITE[23]	TCC_RW_REQ[24]	TCC_TOO_MANY_EA_WRREQS_STALL[24]	TCC_WRITE[24]	TCC_RW_REQ[25]	TCC_TOO_MANY_EA_WRREQS_STALL[25]	TCC_WRITE[25]	TCC_RW_REQ[26]	TCC_TOO_MANY_EA_WRREQS_STALL[26]	TCC_WRITE[26]	TCC_RW_REQ[27]	TCC_TOO_MANY_EA_WRREQS_STALL[27]	TCC_WRITE[27]	TCC_RW_REQ[28]	TCC_TOO_MANY_EA_WRREQS_STALL[28]	TCC_WRITE[28]	TCC_RW_REQ[29]	TCC_TOO_MANY_EA_WRREQS_STALL[29]	TCC_WRITE[29]	TCC_RW_REQ[30]	TCC_TOO_MANY_EA_WRREQS_STALL[30]	TCC_WRITE[30]	TCC_RW_REQ[31]	TCC_TOO_MANY_EA_WRREQS_STALL[31]	TCC_WRITE[31]	wave_size_6	obj_6	SQ_INSTS_VALU_MUL_F32	SQ_INSTS_VALU_FMA_F32	SQ_INSTS_VALU_TRANS_F32	SQ_INSTS_VALU_ADD_F64	SQ_INSTS_VALU_MUL_F64	SQ_INSTS_VALU_FMA_F64	SQ_INSTS_VALU_TRANS_F64	SQ_INSTS_VALU_INT32	TCP_VOLATILE_sum	TCP_TOTAL_ACCESSES_sum	TCP_TOTAL_READ_sum	TCP_TOTAL_WRITE_sum	TA_BUFFER_ATOMIC_WAVEFRONTS_sum	TA_BUFFER_TOTAL_CYCLES_sum	TD_ATOMIC_WAVEFRONT_sum	TD_STORE_WAVEFRONT_sum	SPI_RA_REQ_NO_ALLOC	SPI_RA_REQ_NO_ALLOC_CSN	CPC_CPC_STAT_STALL	CPC_UTCL1_STALL_ON_TRANSLATION	CPF_CPF_STAT_IDLE	CPF_CPF_TCIU_IDLE	TCC_REQ_sum	TCC_STREAMING_REQ_sum	TCC_HIT_sum	TCC_MISS_sum	wave_size_7	obj_7	TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]	TCC_EA_WRREQ_GMI_CREDIT_STALL[0]	TCC_EA_WRREQ_IO_CREDIT_STALL[0]	TCC_EA_WRREQ_LEVEL[0]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]	TCC_EA_WRREQ_GMI_CREDIT_STALL[1]	TCC_EA_WRREQ_IO_CREDIT_STALL[1]	TCC_EA_WRREQ_LEVEL[1]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]	TCC_EA_WRREQ_GMI_CREDIT_STALL[2]	TCC_EA_WRREQ_IO_CREDIT_STALL[2]	TCC_EA_WRREQ_LEVEL[2]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]	TCC_EA_WRREQ_GMI_CREDIT_STALL[3]	TCC_EA_WRREQ_IO_CREDIT_STALL[3]	TCC_EA_WRREQ_LEVEL[3]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]	TCC_EA_WRREQ_GMI_CREDIT_STALL[4]	TCC_EA_WRREQ_IO_CREDIT_STALL[4]	TCC_EA_WRREQ_LEVEL[4]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]	TCC_EA_WRREQ_GMI_CREDIT_STALL[5]	TCC_EA_WRREQ_IO_CREDIT_STALL[5]	TCC_EA_WRREQ_LEVEL[5]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]	TCC_EA_WRREQ_GMI_CREDIT_STALL[6]	TCC_EA_WRREQ_IO_CREDIT_STALL[6]	TCC_EA_WRREQ_LEVEL[6]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]	TCC_EA_WRREQ_GMI_CREDIT_STALL[7]	TCC_EA_WRREQ_IO_CREDIT_STALL[7]	TCC_EA_WRREQ_LEVEL[7]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]	TCC_EA_WRREQ_GMI_CREDIT_STALL[8]	TCC_EA_WRREQ_IO_CREDIT_STALL[8]	TCC_EA_WRREQ_LEVEL[8]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]	TCC_EA_WRREQ_GMI_CREDIT_STALL[9]	TCC_EA_WRREQ_IO_CREDIT_STALL[9]	TCC_EA_WRREQ_LEVEL[9]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]	TCC_EA_WRREQ_GMI_CREDIT_STALL[10]	TCC_EA_WRREQ_IO_CREDIT_STALL[10]	TCC_EA_WRREQ_LEVEL[10]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]	TCC_EA_WRREQ_GMI_CREDIT_STALL[11]	TCC_EA_WRREQ_IO_CREDIT_STALL[11]	TCC_EA_WRREQ_LEVEL[11]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]	TCC_EA_WRREQ_GMI_CREDIT_STALL[12]	TCC_EA_WRREQ_IO_CREDIT_STALL[12]	TCC_EA_WRREQ_LEVEL[12]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]	TCC_EA_WRREQ_GMI_CREDIT_STALL[13]	TCC_EA_WRREQ_IO_CREDIT_STALL[13]	TCC_EA_WRREQ_LEVEL[13]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]	TCC_EA_WRREQ_GMI_CREDIT_STALL[14]	TCC_EA_WRREQ_IO_CREDIT_STALL[14]	TCC_EA_WRREQ_LEVEL[14]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]	TCC_EA_WRREQ_GMI_CREDIT_STALL[15]	TCC_EA_WRREQ_IO_CREDIT_STALL[15]	TCC_EA_WRREQ_LEVEL[15]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]	TCC_EA_WRREQ_GMI_CREDIT_STALL[16]	TCC_EA_WRREQ_IO_CREDIT_STALL[16]	TCC_EA_WRREQ_LEVEL[16]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]	TCC_EA_WRREQ_GMI_CREDIT_STALL[17]	TCC_EA_WRREQ_IO_CREDIT_STALL[17]	TCC_EA_WRREQ_LEVEL[17]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]	TCC_EA_WRREQ_GMI_CREDIT_STALL[18]	TCC_EA_WRREQ_IO_CREDIT_STALL[18]	TCC_EA_WRREQ_LEVEL[18]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]	TCC_EA_WRREQ_GMI_CREDIT_STALL[19]	TCC_EA_WRREQ_IO_CREDIT_STALL[19]	TCC_EA_WRREQ_LEVEL[19]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]	TCC_EA_WRREQ_GMI_CREDIT_STALL[20]	TCC_EA_WRREQ_IO_CREDIT_STALL[20]	TCC_EA_WRREQ_LEVEL[20]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]	TCC_EA_WRREQ_GMI_CREDIT_STALL[21]	TCC_EA_WRREQ_IO_CREDIT_STALL[21]	TCC_EA_WRREQ_LEVEL[21]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]	TCC_EA_WRREQ_GMI_CREDIT_STALL[22]	TCC_EA_WRREQ_IO_CREDIT_STALL[22]	TCC_EA_WRREQ_LEVEL[22]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]	TCC_EA_WRREQ_GMI_CREDIT_STALL[23]	TCC_EA_WRREQ_IO_CREDIT_STALL[23]	TCC_EA_WRREQ_LEVEL[23]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]	TCC_EA_WRREQ_GMI_CREDIT_STALL[24]	TCC_EA_WRREQ_IO_CREDIT_STALL[24]	TCC_EA_WRREQ_LEVEL[24]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]	TCC_EA_WRREQ_GMI_CREDIT_STALL[25]	TCC_EA_WRREQ_IO_CREDIT_STALL[25]	TCC_EA_WRREQ_LEVEL[25]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]	TCC_EA_WRREQ_GMI_CREDIT_STALL[26]	TCC_EA_WRREQ_IO_CREDIT_STALL[26]	TCC_EA_WRREQ_LEVEL[26]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]	TCC_EA_WRREQ_GMI_CREDIT_STALL[27]	TCC_EA_WRREQ_IO_CREDIT_STALL[27]	TCC_EA_WRREQ_LEVEL[27]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]	TCC_EA_WRREQ_GMI_CREDIT_STALL[28]	TCC_EA_WRREQ_IO_CREDIT_STALL[28]	TCC_EA_WRREQ_LEVEL[28]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]	TCC_EA_WRREQ_GMI_CREDIT_STALL[29]	TCC_EA_WRREQ_IO_CREDIT_STALL[29]	TCC_EA_WRREQ_LEVEL[29]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]	TCC_EA_WRREQ_GMI_CREDIT_STALL[30]	TCC_EA_WRREQ_IO_CREDIT_STALL[30]	TCC_EA_WRREQ_LEVEL[30]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]	TCC_EA_WRREQ_GMI_CREDIT_STALL[31]	TCC_EA_WRREQ_IO_CREDIT_STALL[31]	TCC_EA_WRREQ_LEVEL[31]	wave_size_8	obj_8	SQ_THREAD_CYCLES_VALU	SQ_IFETCH	SQ_LDS_BANK_CONFLICT	SQ_LDS_ADDR_CONFLICT	SQ_LDS_UNALIGNED_STALL	SQ_WAVES_EQ_64	SQ_WAVES_LT_64	SQ_WAVES_LT_48	TCP_TCC_WRITE_REQ_sum	TCP_TCC_ATOMIC_WITH_RET_REQ_sum	TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum	TCP_TCC_NC_READ_REQ_sum	TA_FLAT_WAVEFRONTS_sum	TA_FLAT_READ_WAVEFRONTS_sum	SPI_RA_BAR_CU_FULL_CSN	SPI_RA_TGLIM_CU_FULL_CSN	TCC_EA_RDREQ_DRAM_sum	TCC_TAG_STALL_sum	TCC_NORMAL_WRITEBACK_sum	TCC_ALL_TC_OP_WB_WRITEBACK_sum	wave_size_9	obj_9	SQ_CYCLES	SQ_BUSY_CYCLES	SQ_WAVES	SQ_INSTS_VALU_CVT	SQ_INSTS_VMEM_WR	SQ_INSTS_VMEM_RD	SQ_INSTS_VMEM	SQ_INSTS_SALU	GRBM_COUNT	GRBM_GUI_ACTIVE	TCP_GATE_EN1_sum	TCP_GATE_EN2_sum	TCP_TD_TCP_STALL_CYCLES_sum	TCP_TCR_TCP_STALL_CYCLES_sum	TA_TA_BUSY_sum	TA_BUFFER_WAVEFRONTS_sum	TD_TD_BUSY_sum	TD_TC_STALL_sum	SPI_CSN_WINDOW_VALID	SPI_CSN_BUSY	CPC_CPC_STAT_BUSY	CPC_CPC_STAT_IDLE	CPF_CPF_STAT_BUSY	CPF_CPF_STAT_STALL	TCC_CYCLE_sum	TCC_BUSY_sum	TCC_PROBE_sum	TCC_PROBE_ALL_sum	wave_size_10	obj_10	SQ_WAVES_LT_32	SQ_WAVES_LT_16	SQ_ITEMS	SQ_LDS_MEM_VIOLATIONS	SQ_LDS_ATOMIC_RETURN	SQ_LDS_IDX_ACTIVE	SQ_WAVES_RESTORED	SQ_WAVES_SAVED	TCP_TCC_NC_WRITE_REQ_sum	TCP_TCC_NC_ATOMIC_REQ_sum	TCP_TCC_UC_READ_REQ_sum	TCP_TCC_UC_WRITE_REQ_sum	TA_FLAT_WRITE_WAVEFRONTS_sum	TA_FLAT_ATOMIC_WAVEFRONTS_sum	SPI_RA_WVLIM_STALL_CSN	SPI_SWC_CSC_WR	TCC_NORMAL_EVICT_sum	TCC_ALL_TC_OP_INV_EVICT_sum	TCC_TOO_MANY_EA_WRREQS_STALL_sum	TCC_EA_ATOMIC_sum	wave_size_11	obj_11	TCC_EA_RDREQ[0]	TCC_EA_RDREQ_32B[0]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]	TCC_EA_RDREQ_GMI_CREDIT_STALL[0]	TCC_EA_RDREQ[1]	TCC_EA_RDREQ_32B[1]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]	TCC_EA_RDREQ_GMI_CREDIT_STALL[1]	TCC_EA_RDREQ[2]	TCC_EA_RDREQ_32B[2]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]	TCC_EA_RDREQ_GMI_CREDIT_STALL[2]	TCC_EA_RDREQ[3]	TCC_EA_RDREQ_32B[3]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]	TCC_EA_RDREQ_GMI_CREDIT_STALL[3]	TCC_EA_RDREQ[4]	TCC_EA_RDREQ_32B[4]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]	TCC_EA_RDREQ_GMI_CREDIT_STALL[4]	TCC_EA_RDREQ[5]	TCC_EA_RDREQ_32B[5]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]	TCC_EA_RDREQ_GMI_CREDIT_STALL[5]	TCC_EA_RDREQ[6]	TCC_EA_RDREQ_32B[6]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]	TCC_EA_RDREQ_GMI_CREDIT_STALL[6]	TCC_EA_RDREQ[7]	TCC_EA_RDREQ_32B[7]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]	TCC_EA_RDREQ_GMI_CREDIT_STALL[7]	TCC_EA_RDREQ[8]	TCC_EA_RDREQ_32B[8]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]	TCC_EA_RDREQ_GMI_CREDIT_STALL[8]	TCC_EA_RDREQ[9]	TCC_EA_RDREQ_32B[9]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]	TCC_EA_RDREQ_GMI_CREDIT_STALL[9]	TCC_EA_RDREQ[10]	TCC_EA_RDREQ_32B[10]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]	TCC_EA_RDREQ_GMI_CREDIT_STALL[10]	TCC_EA_RDREQ[11]	TCC_EA_RDREQ_32B[11]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]	TCC_EA_RDREQ_GMI_CREDIT_STALL[11]	TCC_EA_RDREQ[12]	TCC_EA_RDREQ_32B[12]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]	TCC_EA_RDREQ_GMI_CREDIT_STALL[12]	TCC_EA_RDREQ[13]	TCC_EA_RDREQ_32B[13]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]	TCC_EA_RDREQ_GMI_CREDIT_STALL[13]	TCC_EA_RDREQ[14]	TCC_EA_RDREQ_32B[14]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]	TCC_EA_RDREQ_GMI_CREDIT_STALL[14]	TCC_EA_RDREQ[15]	TCC_EA_RDREQ_32B[15]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]	TCC_EA_RDREQ_GMI_CREDIT_STALL[15]	TCC_EA_RDREQ[16]	TCC_EA_RDREQ_32B[16]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]	TCC_EA_RDREQ_GMI_CREDIT_STALL[16]	TCC_EA_RDREQ[17]	TCC_EA_RDREQ_32B[17]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]	TCC_EA_RDREQ_GMI_CREDIT_STALL[17]	TCC_EA_RDREQ[18]	TCC_EA_RDREQ_32B[18]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]	TCC_EA_RDREQ_GMI_CREDIT_STALL[18]	TCC_EA_RDREQ[19]	TCC_EA_RDREQ_32B[19]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]	TCC_EA_RDREQ_GMI_CREDIT_STALL[19]	TCC_EA_RDREQ[20]	TCC_EA_RDREQ_32B[20]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]	TCC_EA_RDREQ_GMI_CREDIT_STALL[20]	TCC_EA_RDREQ[21]	TCC_EA_RDREQ_32B[21]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]	TCC_EA_RDREQ_GMI_CREDIT_STALL[21]	TCC_EA_RDREQ[22]	TCC_EA_RDREQ_32B[22]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]	TCC_EA_RDREQ_GMI_CREDIT_STALL[22]	TCC_EA_RDREQ[23]	TCC_EA_RDREQ_32B[23]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]	TCC_EA_RDREQ_GMI_CREDIT_STALL[23]	TCC_EA_RDREQ[24]	TCC_EA_RDREQ_32B[24]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]	TCC_EA_RDREQ_GMI_CREDIT_STALL[24]	TCC_EA_RDREQ[25]	TCC_EA_RDREQ_32B[25]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]	TCC_EA_RDREQ_GMI_CREDIT_STALL[25]	TCC_EA_RDREQ[26]	TCC_EA_RDREQ_32B[26]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]	TCC_EA_RDREQ_GMI_CREDIT_STALL[26]	TCC_EA_RDREQ[27]	TCC_EA_RDREQ_32B[27]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]	TCC_EA_RDREQ_GMI_CREDIT_STALL[27]	TCC_EA_RDREQ[28]	TCC_EA_RDREQ_32B[28]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]	TCC_EA_RDREQ_GMI_CREDIT_STALL[28]	TCC_EA_RDREQ[29]	TCC_EA_RDREQ_32B[29]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]	TCC_EA_RDREQ_GMI_CREDIT_STALL[29]	TCC_EA_RDREQ[30]	TCC_EA_RDREQ_32B[30]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]	TCC_EA_RDREQ_GMI_CREDIT_STALL[30]	TCC_EA_RDREQ[31]	TCC_EA_RDREQ_32B[31]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]	TCC_EA_RDREQ_GMI_CREDIT_STALL[31]	wave_size_12	obj_12	SQ_INSTS_VALU_INT64	SQ_INSTS_SMEM	SQ_INSTS_FLAT	SQ_INSTS_LDS	SQ_INSTS_GDS	SQ_INSTS_EXP_GDS	SQ_INSTS_BRANCH	SQ_INSTS_SENDMSG	TCP_TOTAL_ATOMIC_WITH_RET_sum	TCP_TOTAL_ATOMIC_WITHOUT_RET_sum	TCP_TOTAL_WRITEBACK_INVALIDATES_sum	TCP_TOTAL_CACHE_ACCESSES_sum	TA_BUFFER_COALESCED_READ_CYCLES_sum	TA_BUFFER_COALESCED_WRITE_CYCLES_sum	TD_COALESCABLE_WAVEFRONT_sum	SPI_RA_RES_STALL_CSN	SPI_RA_TMP_STALL_CSN	CPC_CPC_UTCL2IU_BUSY	CPC_CPC_UTCL2IU_IDLE	CPF_CMP_UTCL1_STALL_ON_TRANSLATION	TCC_READ_sum	TCC_WRITE_sum	TCC_ATOMIC_sum	TCC_WRITEBACK_sum	wave_size_13	obj_13	TCC_HIT[0]	TCC_MISS[0]	TCC_READ[0]	TCC_REQ[0]	TCC_HIT[1]	TCC_MISS[1]	TCC_READ[1]	TCC_REQ[1]	TCC_HIT[2]	TCC_MISS[2]	TCC_READ[2]	TCC_REQ[2]	TCC_HIT[3]	TCC_MISS[3]	TCC_READ[3]	TCC_REQ[3]	TCC_HIT[4]	TCC_MISS[4]	TCC_READ[4]	TCC_REQ[4]	TCC_HIT[5]	TCC_MISS[5]	TCC_READ[5]	TCC_REQ[5]	TCC_HIT[6]	TCC_MISS[6]	TCC_READ[6]	TCC_REQ[6]	TCC_HIT[7]	TCC_MISS[7]	TCC_READ[7]	TCC_REQ[7]	TCC_HIT[8]	TCC_MISS[8]	TCC_READ[8]	TCC_REQ[8]	TCC_HIT[9]	TCC_MISS[9]	TCC_READ[9]	TCC_REQ[9]	TCC_HIT[10]	TCC_MISS[10]	TCC_READ[10]	TCC_REQ[10]	TCC_HIT[11]	TCC_MISS[11]	TCC_READ[11]	TCC_REQ[11]	TCC_HIT[12]	TCC_MISS[12]	TCC_READ[12]	TCC_REQ[12]	TCC_HIT[13]	TCC_MISS[13]	TCC_READ[13]	TCC_REQ[13]	TCC_HIT[14]	TCC_MISS[14]	TCC_READ[14]	TCC_REQ[14]	TCC_HIT[15]	TCC_MISS[15]	TCC_READ[15]	TCC_REQ[15]	TCC_HIT[16]	TCC_MISS[16]	TCC_READ[16]	TCC_REQ[16]	TCC_HIT[17]	TCC_MISS[17]	TCC_READ[17]	TCC_REQ[17]	TCC_HIT[18]	TCC_MISS[18]	TCC_READ[18]	TCC_REQ[18]	TCC_HIT[19]	TCC_MISS[19]	TCC_READ[19]	TCC_REQ[19]	TCC_HIT[20]	TCC_MISS[20]	TCC_READ[20]	TCC_REQ[20]	TCC_HIT[21]	TCC_MISS[21]	TCC_READ[21]	TCC_REQ[21]	TCC_HIT[22]	TCC_MISS[22]	TCC_READ[22]	TCC_REQ[22]	TCC_HIT[23]	TCC_MISS[23]	TCC_READ[23]	TCC_REQ[23]	TCC_HIT[24]	TCC_MISS[24]	TCC_READ[24]	TCC_REQ[24]	TCC_HIT[25]	TCC_MISS[25]	TCC_READ[25]	TCC_REQ[25]	TCC_HIT[26]	TCC_MISS[26]	TCC_READ[26]	TCC_REQ[26]	TCC_HIT[27]	TCC_MISS[27]	TCC_READ[27]	TCC_REQ[27]	TCC_HIT[28]	TCC_MISS[28]	TCC_READ[28]	TCC_REQ[28]	TCC_HIT[29]	TCC_MISS[29]	TCC_READ[29]	TCC_REQ[29]	TCC_HIT[30]	TCC_MISS[30]	TCC_READ[30]	TCC_REQ[30]	TCC_HIT[31]	TCC_MISS[31]	TCC_READ[31]	TCC_REQ[31]	wave_size_14	obj_14	SQ_INSTS_FLAT_LDS_ONLY	SQ_INSTS_VALU_MFMA_MOPS_I8	SQ_INSTS_VALU_MFMA_MOPS_F16	SQ_INSTS_VALU_MFMA_MOPS_BF16	SQ_INSTS_VALU_MFMA_MOPS_F32	SQ_INSTS_VALU_MFMA_MOPS_F64	SQC_TC_INST_REQ	SQC_TC_DATA_READ_REQ	TCP_TCC_RW_READ_REQ_sum	TCP_TCC_RW_WRITE_REQ_sum	TCP_TCC_RW_ATOMIC_REQ_sum	TCP_PENDING_STALL_CYCLES_sum	wave_size_15	obj_15	SQC_DCACHE_REQ_READ_1	SQC_DCACHE_REQ_READ_2	SQC_DCACHE_REQ_READ_4	wave_size_16	obj_16	SQ_WAVE_CYCLES	SQ_WAIT_ANY	SQ_WAIT_INST_ANY	SQ_ACTIVE_INST_ANY	SQ_BUSY_CU_CYCLES	SQ_ACTIVE_INST_VMEM	SQ_ACTIVE_INST_LDS	SQ_ACTIVE_INST_VALU	TCP_UTCL1_TRANSLATION_MISS_sum	TCP_UTCL1_TRANSLATION_HIT_sum	TCP_UTCL1_PERMISSION_MISS_sum	TCP_UTCL1_REQUEST_sum	TA_ADDR_STALLED_BY_TC_CYCLES_sum	TA_TOTAL_WAVEFRONTS_sum	SPI_RA_WAVE_SIMD_FULL_CSN	SPI_RA_VGPR_SIMD_FULL_CSN	CPC_CPC_UTCL2IU_STALL	CPC_ME1_BUSY_FOR_PACKET_DECODE	TCC_EA_WRREQ_sum	TCC_EA_WRREQ_64B_sum	TCC_EA_WR_UNCACHED_32B_sum	TCC_EA_WRREQ_DRAM_sum	wave_size_17	obj_17	TCC_EA_RDREQ_IO_CREDIT_STALL[0]	TCC_EA_RDREQ_LEVEL[0]	TCC_EA_WRREQ[0]	TCC_EA_WRREQ_64B[0]	TCC_EA_RDREQ_IO_CREDIT_STALL[1]	TCC_EA_RDREQ_LEVEL[1]	TCC_EA_WRREQ[1]	TCC_EA_WRREQ_64B[1]	TCC_EA_RDREQ_IO_CREDIT_STALL[2]	TCC_EA_RDREQ_LEVEL[2]	TCC_EA_WRREQ[2]	TCC_EA_WRREQ_64B[2]	TCC_EA_RDREQ_IO_CREDIT_STALL[3]	TCC_EA_RDREQ_LEVEL[3]	TCC_EA_WRREQ[3]	TCC_EA_WRREQ_64B[3]	TCC_EA_RDREQ_IO_CREDIT_STALL[4]	TCC_EA_RDREQ_LEVEL[4]	TCC_EA_WRREQ[4]	TCC_EA_WRREQ_64B[4]	TCC_EA_RDREQ_IO_CREDIT_STALL[5]	TCC_EA_RDREQ_LEVEL[5]	TCC_EA_WRREQ[5]	TCC_EA_WRREQ_64B[5]	TCC_EA_RDREQ_IO_CREDIT_STALL[6]	TCC_EA_RDREQ_LEVEL[6]	TCC_EA_WRREQ[6]	TCC_EA_WRREQ_64B[6]	TCC_EA_RDREQ_IO_CREDIT_STALL[7]	TCC_EA_RDREQ_LEVEL[7]	TCC_EA_WRREQ[7]	TCC_EA_WRREQ_64B[7]	TCC_EA_RDREQ_IO_CREDIT_STALL[8]	TCC_EA_RDREQ_LEVEL[8]	TCC_EA_WRREQ[8]	TCC_EA_WRREQ_64B[8]	TCC_EA_RDREQ_IO_CREDIT_STALL[9]	TCC_EA_RDREQ_LEVEL[9]	TCC_EA_WRREQ[9]	TCC_EA_WRREQ_64B[9]	TCC_EA_RDREQ_IO_CREDIT_STALL[10]	TCC_EA_RDREQ_LEVEL[10]	TCC_EA_WRREQ[10]	TCC_EA_WRREQ_64B[10]	TCC_EA_RDREQ_IO_CREDIT_STALL[11]	TCC_EA_RDREQ_LEVEL[11]	TCC_EA_WRREQ[11]	TCC_EA_WRREQ_64B[11]	TCC_EA_RDREQ_IO_CREDIT_STALL[12]	TCC_EA_RDREQ_LEVEL[12]	TCC_EA_WRREQ[12]	TCC_EA_WRREQ_64B[12]	TCC_EA_RDREQ_IO_CREDIT_STALL[13]	TCC_EA_RDREQ_LEVEL[13]	TCC_EA_WRREQ[13]	TCC_EA_WRREQ_64B[13]	TCC_EA_RDREQ_IO_CREDIT_STALL[14]	TCC_EA_RDREQ_LEVEL[14]	TCC_EA_WRREQ[14]	TCC_EA_WRREQ_64B[14]	TCC_EA_RDREQ_IO_CREDIT_STALL[15]	TCC_EA_RDREQ_LEVEL[15]	TCC_EA_WRREQ[15]	TCC_EA_WRREQ_64B[15]	TCC_EA_RDREQ_IO_CREDIT_STALL[16]	TCC_EA_RDREQ_LEVEL[16]	TCC_EA_WRREQ[16]	TCC_EA_WRREQ_64B[16]	TCC_EA_RDREQ_IO_CREDIT_STALL[17]	TCC_EA_RDREQ_LEVEL[17]	TCC_EA_WRREQ[17]	TCC_EA_WRREQ_64B[17]	TCC_EA_RDREQ_IO_CREDIT_STALL[18]	TCC_EA_RDREQ_LEVEL[18]	TCC_EA_WRREQ[18]	TCC_EA_WRREQ_64B[18]	TCC_EA_RDREQ_IO_CREDIT_STALL[19]	TCC_EA_RDREQ_LEVEL[19]	TCC_EA_WRREQ[19]	TCC_EA_WRREQ_64B[19]	TCC_EA_RDREQ_IO_CREDIT_STALL[20]	TCC_EA_RDREQ_LEVEL[20]	TCC_EA_WRREQ[20]	TCC_EA_WRREQ_64B[20]	TCC_EA_RDREQ_IO_CREDIT_STALL[21]	TCC_EA_RDREQ_LEVEL[21]	TCC_EA_WRREQ[21]	TCC_EA_WRREQ_64B[21]	TCC_EA_RDREQ_IO_CREDIT_STALL[22]	TCC_EA_RDREQ_LEVEL[22]	TCC_EA_WRREQ[22]	TCC_EA_WRREQ_64B[22]	TCC_EA_RDREQ_IO_CREDIT_STALL[23]	TCC_EA_RDREQ_LEVEL[23]	TCC_EA_WRREQ[23]	TCC_EA_WRREQ_64B[23]	TCC_EA_RDREQ_IO_CREDIT_STALL[24]	TCC_EA_RDREQ_LEVEL[24]	TCC_EA_WRREQ[24]	TCC_EA_WRREQ_64B[24]	TCC_EA_RDREQ_IO_CREDIT_STALL[25]	TCC_EA_RDREQ_LEVEL[25]	TCC_EA_WRREQ[25]	TCC_EA_WRREQ_64B[25]	TCC_EA_RDREQ_IO_CREDIT_STALL[26]	TCC_EA_RDREQ_LEVEL[26]	TCC_EA_WRREQ[26]	TCC_EA_WRREQ_64B[26]	TCC_EA_RDREQ_IO_CREDIT_STALL[27]	TCC_EA_RDREQ_LEVEL[27]	TCC_EA_WRREQ[27]	TCC_EA_WRREQ_64B[27]	TCC_EA_RDREQ_IO_CREDIT_STALL[28]	TCC_EA_RDREQ_LEVEL[28]	TCC_EA_WRREQ[28]	TCC_EA_WRREQ_64B[28]	TCC_EA_RDREQ_IO_CREDIT_STALL[29]	TCC_EA_RDREQ_LEVEL[29]	TCC_EA_WRREQ[29]	TCC_EA_WRREQ_64B[29]	TCC_EA_RDREQ_IO_CREDIT_STALL[30]	TCC_EA_RDREQ_LEVEL[30]	TCC_EA_WRREQ[30]	TCC_EA_WRREQ_64B[30]	TCC_EA_RDREQ_IO_CREDIT_STALL[31]	TCC_EA_RDREQ_LEVEL[31]	TCC_EA_WRREQ[31]	TCC_EA_WRREQ_64B[31]	wave_size_18	obj_18	SQ_INSTS_SMEM_NORM	SQ_INSTS_MFMA	SQ_INSTS_VALU_MFMA_I8	SQ_INSTS_VALU_MFMA_F16	SQ_INSTS_VALU_MFMA_BF16	SQ_INSTS_VALU_MFMA_F32	SQ_INSTS_VALU_MFMA_F64	SQ_VALU_MFMA_BUSY_CYCLES	TCP_TCC_UC_ATOMIC_REQ_sum	TCP_TCC_CC_READ_REQ_sum	TCP_TCC_CC_WRITE_REQ_sum	TCP_TCC_CC_ATOMIC_REQ_sum	SPI_VWC_CSC_WR	SPI_RA_BULKY_CU_FULL_CSN	TCC_EA_RDREQ_LEVEL_sum	TCC_EA_WRREQ_LEVEL_sum	TCC_EA_ATOMIC_LEVEL_sum	Start_Timestamp	End_Timestamp
2	0	vecCopy(double*, double*, double*, int, int)	2	1048576	256	0	0	8	0	16	64	0x7f4a2fab8ec0	0	393216	163840	0	0	0	0	0	18187	0.0	0.0	0.0	32768.0	0.0	0.0	395.0	32768.0	4096	16384	352	28609	2100	0	56.0	8.0	0.0	204428.0	64	0x7f47e819cec0	114688	0	32768	32768	16384	16384	65536	49152	27519246.0	86577439.0	38720502.0	131072.0	0.0	233918.0	0	0	15372	569.0	131086.0	0.0	20.0	64	0x7f7e08b40ec0	1275	121672	0	0	65536	63800	56	1680	64	0x7fc86bf10ec0	0	0	0	224	0	65536	64213	56	64	0x7f0cb3310ec0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	0	27535	0	0	64	0x7f892acf0ec0	6414	0	4096	6385	0	4096	6373	0	4096	6358	0	4096	6385	0	4096	6411	0	4096	6361	0	4096	6376	0	4096	6378	0	4096	6417	0	4096	6382	0	4096	6375	0	4096	6356	0	4096	6390	0	4096	6413	0	4096	6357	0	4096	6349	0	4096	6381	0	4096	6399	0	4096	6394	0	4096	6388	0	4096	6409	0	4096	6399	0	4096	6535	0	4096	6365	0	4096	6354	0	4096	6381	0	4096	6401	0	4096	6395	0	4096	6392	0	4096	6406	0	4096	6403	0	4096	64	0x7f84b8ac4ec0	0	0	0	0	0	0	0	114688	2097152.0	2097152.0	1048576.0	1048576.0	0.0	0.0	0.0	16384.0	13682	19128	8188	551	0	27229	204211.0	0.0	73130.0	131081.0	64	0x7f7f3b020ec0	0	0	0	1060632	13	0	0	1275584	0	0	0	999915	0	0	0	1129505	0	0	0	1096028	0	0	0	1055633	0	0	0	985615	0	0	0	1234953	0	0	0	1032049	0	0	0	1020348	0	0	0	1096685	0	0	0	1088182	0	0	0	1029177	0	0	0	1135761	0	0	0	1135865	0	0	0	1084249	73	0	0	1155288	0	0	0	977888	0	0	0	1141547	15	0	0	1316407	0	0	0	1050000	0	0	0	1195803	0	0	0	1036194	0	0	0	1066018	0	0	0	1046708	0	0	0	1012012	0	0	0	1007663	0	0	0	1164332	26	0	0	1180856	0	0	0	1034428	0	0	0	1023008	0	0	0	1251564	64	0x7f8fb71f8ec0	10485760	65536	0	0	0	16384	0	0	131072.0	0.0	0.0	0.0	32768.0	16384.0	0	0	131083.0	34785.0	46209.0	19327.0	64	0x7f2960af4ec0	217216	125479	16384	0	16384	16384	32768	49152	27151	27151	1909016.0	1326876.0	3429.0	167194.0	1033159.0	0.0	1319211.0	1021505.0	215505	133626	27151	0	27151	0	868832.0	480116.0	0.0	0.0	64	0x7f7aa37f8ec0	0	0	1048576	0	0	0	0	0	0.0	0.0	0.0	0.0	16384.0	0.0	0	32768	65551.0	0.0	0.0	0.0	64	0x7fdf23204ec0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4097	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4098	0	0	0	4097	0	0	0	4096	0	7	0	4096	0	0	0	4097	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4099	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	4096	0	0	0	64	0x7f8f6cdf8ec0	0	65536	32768	0	0	0	16384	16384	0.0	0.0	0.0	524288.0	0.0	0.0	0.0	10836	0	819	28703	0	73230.0	131072.0	0.0	65568.0	64	0x7f724b4e8ec0	2253	4096	2253	6349	2274	4096	2274	6370	2315	4097	2316	6412	2279	4096	2279	6375	2244	4096	2244	6340	2300	4096	2300	6396	2258	4096	2258	6354	2285	4096	2285	6381	2286	4096	2286	6382	2253	4096	2253	6349	2271	4096	2271	6367	2261	4096	2261	6357	2281	4096	2281	6377	2246	4096	2246	6342	2300	4096	2300	6396	2262	4096	2262	6358	2263	4096	2263	6359	2288	4097	2289	6385	2283	4097	2284	6380	2277	4096	2277	6373	2303	4096	2303	6399	2239	4096	2239	6335	2290	4096	2290	6386	2469	4098	2471	6567	2297	4096	2297	6393	2265	4096	2265	6361	2287	4096	2287	6383	2287	4098	2289	6385	2283	4096	2283	6379	2305	4096	2305	6401	2245	4096	2245	6341	2290	4096	2290	6386	64	0x7fd8c4d90ec0	0	0	0	0	0	0	168	56	131072.0	131072.0	0.0	980822.0	64	0x7f2bf9774ec0	32768	32768	0	64	0x7f18be1d8ec0	11168674	9922713	901897	344064	1680292	0	0	163840	832.0	515136.0	0.0	524288.0	286559.0	32768.0	529152	0	0	10665	131072.0	131072.0	0.0	131072.0	64	0x7efd92da0ec0	0	1112958	4096	4096	0	1464234	4096	4096	0	1294198	4096	4096	0	1321579	4096	4096	0	1193151	4096	4096	0	1435597	4096	4096	0	1087935	4096	4096	0	1413763	4096	4096	0	1090049	4096	4096	0	1189635	4096	4096	0	1151982	4096	4096	0	1187887	4096	4096	0	1147006	4096	4096	0	1183703	4096	4096	0	1322546	4096	4096	0	1114940	4096	4096	0	1336345	4096	4096	0	1001566	4096	4096	0	1160359	4096	4096	0	1503085	4096	4096	0	1283481	4096	4096	0	1245318	4096	4096	0	1255709	4096	4096	0	1139847	4096	4096	0	1292855	4096	4096	0	1204703	4096	4096	0	1037434	4096	4096	0	1174830	4096	4096	0	1143410	4096	4096	0	1185666	4096	4096	0	1136483	4096	4096	0	1513929	4096	4096	64	0x7f029f7e8ec0	131072	0	0	0	0	0	0	0	0.0	0.0	0.0	0.0	16384	0	39362136.0	34460235.0	0.0	198609512940794	198609512961274
3	1	vecCopy(double*, double*, double*, int, int)	2	1048576	256	0	0	8	0	16	64	0x7f4a2fab8ec0	0	393216	163840	0	0	0	0	0	28273	0.0	0.0	0.0	32768.0	0.0	0.0	264.0	32768.0	4096	16384	302	37505	2061	0	56.0	0.0	0.0	200647.0	64	0x7f47e819cec0	114688	0	32768	32768	16384	16384	65536	49152	58351689.0	199740715.0	47356153.0	131072.0	0.0	608661.0	0	0	25624	25352.0	131085.0	0.0	24.0	64	0x7f7e08b40ec0	0	211412	0	0	65536	63800	56	1680	64	0x7fc86bf10ec0	0	0	0	56	0	65536	65536	0	64	0x7f0cb3310ec0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	0	41834	0	0	64	0x7f892acf0ec0	6290	0	4096	6278	0	4096	6285	0	4096	6258	0	4096	6260	0	4096	6250	0	4096	6296	0	4096	6269	0	4096	6274	0	4096	6289	0	4096	6279	0	4096	6286	0	4096	6262	0	4096	6263	0	4096	6252	0	4096	6299	0	4096	6278	0	4096	6277	0	4096	6276	0	4096	6286	0	4096	6254	0	4096	6236	0	4096	6275	0	4096	6274	0	4096	6274	0	4096	6281	0	4096	6275	0	4096	6278	0	4096	6284	0	4096	6252	0	4096	6246	0	4096	6272	0	4096	64	0x7f84b8ac4ec0	0	0	0	0	0	0	0	114688	2097152.0	2097152.0	1048576.0	1048576.0	0.0	0.0	0.0	16384.0	35266	28104	9579	2829	0	41038	200795.0	0.0	69712.0	131083.0	64	0x7f7f3b020ec0	138	0	0	1807628	0	0	0	1827498	165	0	0	2227358	181	0	0	2120664	0	0	0	1497979	912	0	0	2223527	0	0	0	1933367	176	0	0	2159154	0	0	0	1909110	236	0	0	1643335	0	0	0	1638015	501	0	0	1947456	325	0	0	1837027	0	0	0	1461520	32	0	0	1944737	0	0	0	1874947	0	0	0	1657958	22	0	0	2204591	0	0	0	1540041	399	0	0	1860741	146	0	0	1686425	143	0	0	2245703	0	0	0	1437395	0	0	0	1645404	0	0	0	1619523	0	0	0	1641243	521	0	0	2152628	0	0	0	1950767	64	0	0	1549545	150	0	0	1695926	202	0	0	1685968	0	0	0	1777436	64	0x7f8fb71f8ec0	10485760	65536	0	0	0	16384	0	0	131072.0	0.0	0.0	0.0	32768.0	16384.0	0	0	131084.0	92912.0	45614.0	0.0	64	0x7f2960af4ec0	331880	223650	16384	0	16384	16384	32768	49152	41484	41484	3184756.0	2511449.0	4735.0	382351.0	1781220.0	0.0	2499517.0	2190353.0	331872	232947	41484	0	41484	0	1327488.0	796855.0	0.0	0.0	64	0x7f7aa37f8ec0	0	0	1048576	0	0	0	0	0	0.0	0.0	0.0	0.0	16384.0	0.0	0	32768	65550.0	0.0	0.0	0.0	64	0x7fdf23204ec0	4096	0	468	0	4096	0	607	0	4096	0	1338	0	4096	0	532	0	4096	0	17	0	4096	0	111	0	4097	0	422	0	4096	0	1350	0	4096	0	1020	0	4096	0	226	0	4096	0	492	0	4097	0	1202	0	4096	0	997	0	4096	0	454	0	4098	0	1599	0	4097	0	1215	0	4096	0	227	0	4096	0	536	0	4097	0	244	0	4096	0	629	0	4096	0	305	0	4096	0	667	0	4096	0	315	0	4096	0	1196	0	4096	0	219	0	4096	0	956	0	4096	0	223	0	4097	0	141	0	4096	0	318	0	4098	0	133	0	4096	0	43	0	4096	0	10	0	64	0x7f8f6cdf8ec0	0	65536	32768	0	0	0	16384	16384	0.0	0.0	0.0	524288.0	0.0	0.0	0.0	15530	0	819	36227	0	69653.0	131072.0	0.0	45684.0	64	0x7f724b4e8ec0	2158	4097	2159	6255	2151	4096	2151	6247	2265	4097	2266	6362	2175	4096	2175	6271	2158	4096	2158	6254	2161	4097	2162	6258	2165	4096	2165	6261	2152	4096	2152	6248	2154	4096	2154	6250	2160	4097	2161	6257	2154	4096	2154	6250	2210	4096	2210	6306	2177	4096	2177	6273	2158	4096	2158	6254	2159	4096	2159	6255	2169	4096	2169	6265	2170	4096	2170	6266	2137	4097	2138	6234	2153	4098	2155	6251	2151	4096	2151	6247	2158	4096	2158	6254	2203	4096	2203	6299	2164	4096	2164	6260	2164	4096	2164	6260	2170	4096	2170	6266	2171	4096	2171	6267	2137	4096	2137	6233	2152	4098	2154	6250	2151	4096	2151	6247	2158	4096	2158	6254	2205	4096	2205	6301	2169	4096	2169	6265	64	0x7fd8c4d90ec0	0	0	0	0	0	0	0	56	131072.0	131072.0	0.0	2006123.0	64	0x7f2bf9774ec0	32768	32768	0	64	0x7f18be1d8ec0	19514784	18251139	919581	344064	2815906	0	0	163840	832.0	515136.0	0.0	524288.0	603815.0	32768.0	1013862	0	0	13766	91363.0	91363.0	0.0	91363.0	64	0x7efd92da0ec0	0	3426461	2852	2852	0	5196063	2894	2894	0	2808279	2860	2860	0	4040483	2856	2856	0	3772796	2870	2870	0	4040365	2838	2838	0	2840661	2842	2842	0	4380697	2792	2792	0	3625585	2792	2792	0	3694624	2852	2852	0	3192613	2896	2896	0	3174666	2860	2860	0	3270470	2858	2858	0	3538463	2876	2876	0	4660296	2836	2836	0	3792854	2840	2840	0	3855704	2816	2816	0	3029733	2820	2820	0	3888200	2864	2864	0	3951296	2860	2860	0	3411540	2844	2844	0	3724081	2872	2872	0	3666285	2832	2832	0	5354856	2828	2828	0	4530089	2828	2828	0	3023717	2816	2816	0	4697570	2814	2814	0	3849095	2864	2864	0	3167936	2860	2860	0	2773351	2844	2844	0	3706712	2876	2876	0	4062111	2830	2830	64	0x7f029f7e8ec0	131072	0	0	0	0	0	0	0	0.0	0.0	0.0	0.0	16384	0	120455321.0	60544388.0	0.0	198609513046074	198609513062554