Jose Santos
34 KiB
34 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | SQ_INSTS_VALU_MUL_F32 | SQ_INSTS_VALU_FMA_F32 | SQ_INSTS_VALU_TRANS_F32 | SQ_INSTS_VALU_ADD_F64 | SQ_INSTS_VALU_MUL_F64 | SQ_INSTS_VALU_FMA_F64 | SQ_INSTS_VALU_TRANS_F64 | SQ_INSTS_VALU_INT32 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_1 | obj_1 | SQ_WAVE_CYCLES | SQ_WAIT_ANY | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_BUSY_CU_CYCLES | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_2 | obj_2 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_3 | obj_3 | SQC_DCACHE_REQ_READ_1 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | wave_size_4 | obj_4 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | wave_size_5 | obj_5 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_6 | obj_6 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_7 | obj_7 | SQC_TC_DATA_WRITE_REQ | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | wave_size_8 | obj_8 | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | wave_size_9 | obj_9 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_10 | obj_10 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_WAVES | SQ_INSTS_VALU_CVT | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_11 | obj_11 | SQ_INSTS_VALU_INT64 | SQ_INSTS_SMEM | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | TD_COALESCABLE_WAVEFRONT_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_12 | obj_12 | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_13 | obj_13 | SQ_INSTS_VSKIPPED | SQ_INSTS | SQ_INSTS_VALU | SQ_INSTS_VALU_ADD_F16 | SQ_INSTS_VALU_MUL_F16 | SQ_INSTS_VALU_FMA_F16 | SQ_INSTS_VALU_TRANS_F16 | SQ_INSTS_VALU_ADD_F32 | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_SPI_STALL_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_14 | obj_14 | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_DRAM_sum | TCC_TAG_STALL_sum | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | wave_size_15 | obj_15 | SQC_ICACHE_MISSES_DUPLICATE | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | wave_size_16 | obj_16 | SQ_INSTS_SMEM_NORM | SQ_INSTS_MFMA | SQ_INSTS_VALU_MFMA_I8 | SQ_INSTS_VALU_MFMA_F16 | SQ_INSTS_VALU_MFMA_BF16 | SQ_INSTS_VALU_MFMA_F32 | SQ_INSTS_VALU_MFMA_F64 | SQ_VALU_MFMA_BUSY_CYCLES | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | TCC_EA_ATOMIC_LEVEL_sum | wave_size_17 | obj_17 | SQ_INSTS_FLAT_LDS_ONLY | SQ_INSTS_VALU_MFMA_MOPS_I8 | SQ_INSTS_VALU_MFMA_MOPS_F16 | SQ_INSTS_VALU_MFMA_MOPS_BF16 | SQ_INSTS_VALU_MFMA_MOPS_F32 | SQ_INSTS_VALU_MFMA_MOPS_F64 | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | wave_size_18 | obj_18 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f7a5ea30ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 14028 | 19506 | 7920 | 547 | 0 | 27221 | 203514.0 | 0.0 | 72430.0 | 131084.0 | 64 | 0x7f1ae2278ec0 | 10859351 | 9857065 | 658222 | 344064 | 1639415 | 0 | 0 | 163840 | 832.0 | 515136.0 | 0.0 | 524288.0 | 284003.0 | 32768.0 | 485803 | 0 | 0 | 10923 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7f15a5de8ec0 | 0 | 0 | 0 | 956056 | 0 | 0 | 0 | 1011778 | 0 | 0 | 0 | 1136179 | 0 | 0 | 0 | 1189699 | 0 | 0 | 0 | 1104475 | 12 | 0 | 0 | 1152792 | 12 | 0 | 0 | 1145845 | 47 | 0 | 0 | 1300444 | 65 | 0 | 0 | 1238716 | 0 | 0 | 0 | 983608 | 0 | 0 | 0 | 937471 | 0 | 0 | 0 | 1144009 | 0 | 0 | 0 | 1161780 | 0 | 0 | 0 | 1121077 | 0 | 0 | 0 | 1023641 | 0 | 0 | 0 | 1136005 | 0 | 0 | 0 | 1124093 | 5 | 0 | 0 | 1216583 | 0 | 0 | 0 | 1002079 | 12 | 0 | 0 | 1140318 | 0 | 0 | 0 | 1029452 | 196 | 0 | 0 | 1321454 | 0 | 0 | 0 | 1139146 | 0 | 0 | 0 | 1115911 | 0 | 0 | 0 | 1124928 | 0 | 0 | 0 | 1095036 | 0 | 0 | 0 | 1014058 | 0 | 0 | 0 | 1103718 | 0 | 0 | 0 | 1027860 | 0 | 0 | 0 | 1051087 | 0 | 0 | 0 | 1148759 | 0 | 0 | 0 | 1015853 | 64 | 0x7f05f40a0ec0 | 32768 | 32768 | 0 | 64 | 0x7f47183d8ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65551.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7fb8009f8ec0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 0 | 27522 | 0 | 0 | 64 | 0x7f8d37784ec0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 22 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 4 | 0 | 4101 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 34 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 219 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 64 | 0x7fbc26c78ec0 | 0 | 0 | 0 | 224 | 0 | 65536 | 64181 | 56 | 64 | 0x7fed73b94ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 27830943.0 | 88351260.0 | 38720340.0 | 131072.0 | 0.0 | 206725.0 | 0 | 0 | 14875 | 138.0 | 131081.0 | 0.0 | 10.0 | 64 | 0x7f65b5028ec0 | 2231 | 4096 | 2231 | 6327 | 2284 | 4096 | 2284 | 6380 | 2283 | 4096 | 2283 | 6379 | 2286 | 4096 | 2286 | 6382 | 2264 | 4096 | 2264 | 6360 | 2269 | 4097 | 2270 | 6366 | 2294 | 4096 | 2294 | 6390 | 2290 | 4096 | 2290 | 6386 | 2290 | 4096 | 2290 | 6386 | 2232 | 4096 | 2232 | 6328 | 2286 | 4096 | 2286 | 6382 | 2284 | 4096 | 2284 | 6380 | 2286 | 4096 | 2286 | 6382 | 2324 | 4097 | 2325 | 6421 | 2272 | 4096 | 2272 | 6368 | 2293 | 4096 | 2293 | 6389 | 2280 | 4099 | 2283 | 6379 | 2289 | 4096 | 2289 | 6385 | 2243 | 4097 | 2244 | 6340 | 2258 | 4096 | 2258 | 6354 | 2281 | 4096 | 2281 | 6377 | 2325 | 4096 | 2325 | 6421 | 2269 | 4096 | 2269 | 6365 | 2449 | 4098 | 2451 | 6547 | 2285 | 4096 | 2285 | 6381 | 2284 | 4096 | 2284 | 6380 | 2295 | 4096 | 2295 | 6391 | 2243 | 4096 | 2243 | 6339 | 2256 | 4096 | 2256 | 6352 | 2281 | 4096 | 2281 | 6377 | 2327 | 4096 | 2327 | 6423 | 2271 | 4096 | 2271 | 6367 | 64 | 0x7f86b4438ec0 | 222024 | 129283 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 27752 | 27752 | 1958260.0 | 1352086.0 | 3458.0 | 150388.0 | 1064219.0 | 0.0 | 1344454.0 | 1047013.0 | 220313 | 137414 | 27752 | 0 | 27752 | 0 | 888064.0 | 475768.0 | 0.0 | 0.0 | 64 | 0x7f0869250ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 10271 | 0 | 817 | 27847 | 0 | 72952.0 | 131072.0 | 0.0 | 65568.0 | 64 | 0x7f1c3083cec0 | 0 | 1240407 | 4096 | 4096 | 0 | 1293421 | 4096 | 4096 | 0 | 1290782 | 4096 | 4096 | 0 | 1155322 | 4096 | 4096 | 0 | 1145435 | 4096 | 4096 | 0 | 1087237 | 4096 | 4096 | 0 | 1643369 | 4096 | 4096 | 0 | 1264251 | 4096 | 4096 | 0 | 1137249 | 4096 | 4096 | 0 | 1259465 | 4096 | 4096 | 0 | 1230781 | 4096 | 4096 | 0 | 1245523 | 4096 | 4096 | 0 | 1128832 | 4096 | 4096 | 0 | 1138570 | 4096 | 4096 | 0 | 1280799 | 4096 | 4096 | 0 | 1238290 | 4096 | 4096 | 0 | 1057989 | 4096 | 4096 | 0 | 1137603 | 4096 | 4096 | 0 | 1119570 | 4096 | 4096 | 0 | 1501648 | 4096 | 4096 | 0 | 1216808 | 4096 | 4096 | 0 | 1288956 | 4096 | 4096 | 0 | 1162251 | 4096 | 4096 | 0 | 1182789 | 4096 | 4096 | 0 | 1222269 | 4096 | 4096 | 0 | 1023575 | 4096 | 4096 | 0 | 1059677 | 4096 | 4096 | 0 | 1416373 | 4096 | 4096 | 0 | 1365018 | 4096 | 4096 | 0 | 1187606 | 4096 | 4096 | 0 | 1057060 | 4096 | 4096 | 0 | 1306203 | 4096 | 4096 | 64 | 0x7f2d2947cec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 17744 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 405.0 | 32768.0 | 4096 | 16384 | 352 | 28253 | 2231 | 0 | 56.0 | 5.0 | 0.0 | 203801.0 | 64 | 0x7f553b0b0ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131083.0 | 35839.0 | 46120.0 | 19416.0 | 64 | 0x7effc4ae8ec0 | 1257 | 113304 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f123191cec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 41867435.0 | 34832387.0 | 0.0 | 64 | 0x7f637f758ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 168 | 56 | 131072.0 | 131072.0 | 0.0 | 980229.0 | 64 | 0x7fb1db9c4ec0 | 6362 | 0 | 4096 | 6346 | 0 | 4096 | 6375 | 0 | 4096 | 6427 | 0 | 4096 | 6346 | 0 | 4096 | 6364 | 0 | 4096 | 6340 | 0 | 4096 | 6433 | 0 | 4096 | 6436 | 0 | 4096 | 6362 | 0 | 4096 | 6347 | 0 | 4096 | 6376 | 0 | 4096 | 6427 | 0 | 4096 | 6349 | 0 | 4096 | 6363 | 0 | 4096 | 6346 | 0 | 4096 | 6386 | 0 | 4096 | 6392 | 0 | 4096 | 6369 | 0 | 4096 | 6340 | 0 | 4096 | 6382 | 0 | 4096 | 6384 | 0 | 4096 | 6378 | 0 | 4096 | 6520 | 0 | 4096 | 6354 | 0 | 4096 | 6388 | 0 | 4096 | 6393 | 0 | 4096 | 6369 | 0 | 4096 | 6341 | 0 | 4096 | 6382 | 0 | 4096 | 6387 | 0 | 4096 | 6381 | 0 | 4096 | 200174259821413 | 200174259842053 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f7a5ea30ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 27922 | 28136 | 8427 | 550 | 0 | 35389 | 200522.0 | 0.0 | 69447.0 | 131075.0 | 64 | 0x7f1ae2278ec0 | 17699656 | 17126682 | 228910 | 344064 | 2581872 | 0 | 0 | 163840 | 0.0 | 524288.0 | 0.0 | 524288.0 | 456056.0 | 32768.0 | 784400 | 0 | 0 | 11580 | 91294.0 | 91294.0 | 0.0 | 91294.0 | 64 | 0x7f15a5de8ec0 | 0 | 0 | 0 | 1476958 | 0 | 0 | 0 | 1484506 | 0 | 0 | 0 | 2141999 | 380 | 0 | 0 | 2107744 | 0 | 0 | 0 | 1962154 | 80 | 0 | 0 | 1850892 | 71 | 0 | 0 | 1795681 | 0 | 0 | 0 | 1786698 | 0 | 0 | 0 | 1643811 | 0 | 0 | 0 | 1334453 | 46 | 0 | 0 | 1707745 | 0 | 0 | 0 | 1866452 | 0 | 0 | 0 | 1565908 | 0 | 0 | 0 | 1861219 | 390 | 0 | 0 | 2198669 | 0 | 0 | 0 | 1676566 | 0 | 0 | 0 | 1810149 | 0 | 0 | 0 | 1423959 | 0 | 0 | 0 | 1448796 | 0 | 0 | 0 | 1825655 | 0 | 0 | 0 | 1643794 | 156 | 0 | 0 | 1991800 | 367 | 0 | 0 | 1884672 | 13 | 0 | 0 | 1780589 | 70 | 0 | 0 | 1809295 | 0 | 0 | 0 | 1474915 | 0 | 0 | 0 | 1540670 | 0 | 0 | 0 | 1403032 | 0 | 0 | 0 | 1508568 | 0 | 0 | 0 | 1743565 | 30 | 0 | 0 | 1748857 | 0 | 0 | 0 | 1733371 | 64 | 0x7f05f40a0ec0 | 32768 | 32768 | 0 | 64 | 0x7f47183d8ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65550.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7fb8009f8ec0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 0 | 40608 | 0 | 0 | 64 | 0x7f8d37784ec0 | 4096 | 0 | 34 | 0 | 4096 | 0 | 2605 | 0 | 4096 | 0 | 11 | 0 | 4096 | 0 | 700 | 0 | 4096 | 0 | 907 | 0 | 4096 | 0 | 247 | 0 | 4101 | 0 | 30 | 0 | 4096 | 0 | 775 | 0 | 4096 | 0 | 106 | 0 | 4096 | 0 | 381 | 0 | 4096 | 0 | 550 | 0 | 4096 | 0 | 122 | 0 | 4098 | 0 | 309 | 0 | 4096 | 0 | 41 | 0 | 4097 | 0 | 18 | 0 | 4096 | 0 | 94 | 0 | 4096 | 0 | 289 | 0 | 4096 | 0 | 390 | 0 | 4097 | 0 | 274 | 0 | 4096 | 0 | 348 | 0 | 4096 | 0 | 503 | 0 | 4098 | 0 | 797 | 0 | 4097 | 0 | 55 | 0 | 4096 | 0 | 1123 | 0 | 4096 | 0 | 1662 | 0 | 4096 | 0 | 60 | 0 | 4096 | 0 | 64 | 0 | 4096 | 0 | 2765 | 0 | 4096 | 0 | 269 | 0 | 4096 | 0 | 94 | 0 | 4097 | 0 | 379 | 0 | 4096 | 0 | 1029 | 0 | 64 | 0x7fbc26c78ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7fed73b94ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 57504966.0 | 195097391.0 | 47200514.0 | 131072.0 | 0.0 | 543936.0 | 0 | 0 | 25010 | 5335.0 | 131083.0 | 0.0 | 20.0 | 64 | 0x7f65b5028ec0 | 2162 | 4096 | 2162 | 6258 | 2168 | 4096 | 2168 | 6264 | 2131 | 4097 | 2132 | 6228 | 2148 | 4096 | 2148 | 6244 | 2173 | 4096 | 2173 | 6269 | 2171 | 4097 | 2172 | 6268 | 2182 | 4096 | 2182 | 6278 | 2192 | 4096 | 2192 | 6288 | 2196 | 4096 | 2196 | 6292 | 2157 | 4096 | 2157 | 6253 | 2170 | 4096 | 2170 | 6266 | 2135 | 4096 | 2135 | 6231 | 2151 | 4096 | 2151 | 6247 | 2228 | 4097 | 2229 | 6325 | 2168 | 4096 | 2168 | 6264 | 2179 | 4096 | 2179 | 6275 | 2185 | 4098 | 2187 | 6283 | 2173 | 4096 | 2173 | 6269 | 2152 | 4098 | 2154 | 6250 | 2189 | 4096 | 2189 | 6285 | 2131 | 4096 | 2131 | 6227 | 2160 | 4099 | 2163 | 6259 | 2144 | 4096 | 2144 | 6240 | 2173 | 4096 | 2173 | 6269 | 2174 | 4096 | 2174 | 6270 | 2187 | 4096 | 2187 | 6283 | 2177 | 4096 | 2177 | 6273 | 2156 | 4096 | 2156 | 6252 | 2190 | 4096 | 2190 | 6286 | 2130 | 4096 | 2130 | 6226 | 2162 | 4096 | 2162 | 6258 | 2145 | 4096 | 2145 | 6241 | 64 | 0x7f86b4438ec0 | 303000 | 205571 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 37874 | 37874 | 2949719.0 | 2367536.0 | 5033.0 | 364184.0 | 1639574.0 | 0.0 | 2353376.0 | 2042594.0 | 302992 | 214897 | 37874 | 0 | 37874 | 0 | 1211968.0 | 772115.0 | 0.0 | 0.0 | 64 | 0x7f0869250ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 19443 | 0 | 2653 | 38124 | 0 | 69188.0 | 131072.0 | 0.0 | 45562.0 | 64 | 0x7f1c3083cec0 | 0 | 3418781 | 2834 | 2834 | 0 | 3774926 | 2848 | 2848 | 0 | 4291359 | 2864 | 2864 | 0 | 4132082 | 2868 | 2868 | 0 | 3213153 | 2896 | 2896 | 0 | 3716569 | 2860 | 2860 | 0 | 3077725 | 2852 | 2852 | 0 | 3428377 | 2820 | 2820 | 0 | 3256268 | 2820 | 2820 | 0 | 3270489 | 2836 | 2836 | 0 | 3180611 | 2848 | 2848 | 0 | 4050351 | 2864 | 2864 | 0 | 3417258 | 2868 | 2868 | 0 | 3498552 | 2896 | 2896 | 0 | 4442452 | 2864 | 2864 | 0 | 3275478 | 2852 | 2852 | 0 | 3208451 | 2800 | 2800 | 0 | 4007546 | 2840 | 2840 | 0 | 3532965 | 2840 | 2840 | 0 | 3553152 | 2844 | 2844 | 0 | 3406685 | 2830 | 2830 | 0 | 3364811 | 2884 | 2884 | 0 | 5011486 | 2832 | 2832 | 0 | 4303897 | 2836 | 2836 | 0 | 3662817 | 2840 | 2840 | 0 | 4106975 | 2796 | 2796 | 0 | 3504339 | 2840 | 2840 | 0 | 3869973 | 2840 | 2840 | 0 | 4164728 | 2844 | 2844 | 0 | 4763343 | 2832 | 2832 | 0 | 3251083 | 2888 | 2888 | 0 | 4584202 | 2832 | 2832 | 64 | 0x7f2d2947cec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 27486 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 252.0 | 32768.0 | 4096 | 16384 | 302 | 36563 | 2006 | 0 | 56.0 | 0.0 | 0.0 | 199961.0 | 64 | 0x7f553b0b0ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131086.0 | 81674.0 | 45365.0 | 0.0 | 64 | 0x7effc4ae8ec0 | 0 | 187688 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f123191cec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 115073211.0 | 59212179.0 | 0.0 | 64 | 0x7f637f758ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 2025340.0 | 64 | 0x7fb1db9c4ec0 | 6237 | 0 | 4096 | 6257 | 0 | 4096 | 6248 | 0 | 4096 | 6233 | 0 | 4096 | 6273 | 0 | 4096 | 6249 | 0 | 4096 | 6257 | 0 | 4096 | 6256 | 0 | 4096 | 6259 | 0 | 4096 | 6233 | 0 | 4096 | 6259 | 0 | 4096 | 6251 | 0 | 4096 | 6231 | 0 | 4096 | 6280 | 0 | 4096 | 6253 | 0 | 4096 | 6253 | 0 | 4096 | 6261 | 0 | 4096 | 6253 | 0 | 4096 | 6255 | 0 | 4096 | 6280 | 0 | 4096 | 6232 | 0 | 4096 | 6243 | 0 | 4096 | 6237 | 0 | 4096 | 6224 | 0 | 4096 | 6223 | 0 | 4096 | 6264 | 0 | 4096 | 6253 | 0 | 4096 | 6249 | 0 | 4096 | 6276 | 0 | 4096 | 6235 | 0 | 4096 | 6249 | 0 | 4096 | 6238 | 0 | 4096 | 200174259860293 | 200174259876453 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f7a5ea30ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 28576 | 24605 | 9466 | 3198 | 0 | 40300 | 200307.0 | 0.0 | 69220.0 | 131087.0 | 64 | 0x7f1ae2278ec0 | 18686016 | 17546663 | 795289 | 344064 | 2763127 | 0 | 0 | 163840 | 832.0 | 515136.0 | 0.0 | 524288.0 | 601143.0 | 32768.0 | 918208 | 0 | 0 | 12897 | 91150.0 | 91150.0 | 0.0 | 91150.0 | 64 | 0x7f15a5de8ec0 | 0 | 0 | 0 | 1560267 | 0 | 0 | 0 | 1528060 | 0 | 0 | 0 | 1949569 | 0 | 0 | 0 | 1855561 | 0 | 0 | 0 | 1587193 | 2 | 0 | 0 | 1924652 | 536 | 0 | 0 | 2205049 | 99 | 0 | 0 | 1973648 | 0 | 0 | 0 | 1771732 | 0 | 0 | 0 | 1531031 | 388 | 0 | 0 | 1965343 | 0 | 0 | 0 | 1927530 | 0 | 0 | 0 | 1794828 | 0 | 0 | 0 | 2021137 | 0 | 0 | 0 | 1772140 | 95 | 0 | 0 | 2222713 | 0 | 0 | 0 | 1814298 | 90 | 0 | 0 | 1946681 | 0 | 0 | 0 | 1475727 | 0 | 0 | 0 | 1772875 | 163 | 0 | 0 | 2171346 | 0 | 0 | 0 | 1901219 | 183 | 0 | 0 | 1862241 | 0 | 0 | 0 | 2132632 | 0 | 0 | 0 | 1880290 | 0 | 0 | 0 | 1655226 | 5 | 0 | 0 | 1614818 | 0 | 0 | 0 | 1605000 | 183 | 0 | 0 | 2053629 | 0 | 0 | 0 | 1704115 | 0 | 0 | 0 | 1545112 | 0 | 0 | 0 | 1681595 | 64 | 0x7f05f40a0ec0 | 32768 | 32768 | 0 | 64 | 0x7f47183d8ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65554.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7fb8009f8ec0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 0 | 40732 | 0 | 0 | 64 | 0x7f8d37784ec0 | 4096 | 0 | 98 | 0 | 4096 | 0 | 139 | 0 | 4096 | 0 | 1398 | 0 | 4096 | 0 | 1034 | 0 | 4096 | 0 | 2111 | 0 | 4096 | 0 | 969 | 0 | 4101 | 0 | 765 | 0 | 4096 | 0 | 812 | 0 | 4096 | 0 | 381 | 0 | 4096 | 0 | 330 | 0 | 4096 | 0 | 143 | 0 | 4096 | 0 | 245 | 0 | 4098 | 0 | 883 | 0 | 4096 | 0 | 1257 | 0 | 4097 | 0 | 422 | 0 | 4096 | 0 | 590 | 0 | 4096 | 0 | 1248 | 0 | 4096 | 0 | 1616 | 0 | 4097 | 0 | 353 | 0 | 4096 | 0 | 921 | 0 | 4096 | 0 | 214 | 0 | 4098 | 0 | 759 | 0 | 4097 | 0 | 1061 | 0 | 4096 | 0 | 1494 | 0 | 4096 | 0 | 1745 | 0 | 4096 | 0 | 871 | 0 | 4096 | 0 | 567 | 0 | 4096 | 0 | 786 | 0 | 4096 | 0 | 782 | 0 | 4096 | 0 | 421 | 0 | 4097 | 0 | 856 | 0 | 4096 | 0 | 1219 | 0 | 64 | 0x7fbc26c78ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7fed73b94ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 56434754.0 | 202460986.0 | 49754619.0 | 131072.0 | 0.0 | 558592.0 | 0 | 0 | 24814 | 26394.0 | 131085.0 | 0.0 | 24.0 | 64 | 0x7f65b5028ec0 | 2208 | 4096 | 2208 | 6304 | 2220 | 4096 | 2220 | 6316 | 2173 | 4097 | 2174 | 6270 | 2168 | 4096 | 2168 | 6264 | 2157 | 4096 | 2157 | 6253 | 2176 | 4097 | 2177 | 6273 | 2179 | 4096 | 2179 | 6275 | 2173 | 4096 | 2173 | 6269 | 2173 | 4096 | 2173 | 6269 | 2210 | 4096 | 2210 | 6306 | 2215 | 4096 | 2215 | 6311 | 2178 | 4096 | 2178 | 6274 | 2169 | 4096 | 2169 | 6265 | 2215 | 4097 | 2216 | 6312 | 2177 | 4096 | 2177 | 6273 | 2183 | 4096 | 2183 | 6279 | 2177 | 4099 | 2180 | 6276 | 2205 | 4096 | 2205 | 6301 | 2157 | 4098 | 2159 | 6255 | 2223 | 4096 | 2223 | 6319 | 2183 | 4096 | 2183 | 6279 | 2168 | 4099 | 2171 | 6267 | 2156 | 4096 | 2156 | 6252 | 2183 | 4096 | 2183 | 6279 | 2181 | 4096 | 2181 | 6277 | 2180 | 4096 | 2180 | 6276 | 2207 | 4096 | 2207 | 6303 | 2161 | 4096 | 2161 | 6257 | 2225 | 4096 | 2225 | 6321 | 2182 | 4096 | 2182 | 6278 | 2166 | 4096 | 2166 | 6262 | 2152 | 4096 | 2152 | 6248 | 64 | 0x7f86b4438ec0 | 326352 | 219998 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 40793 | 40793 | 3136125.0 | 2454363.0 | 4502.0 | 347779.0 | 1753482.0 | 0.0 | 2443293.0 | 2133873.0 | 326344 | 229021 | 40793 | 0 | 40793 | 0 | 1305376.0 | 762190.0 | 0.0 | 0.0 | 64 | 0x7f0869250ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 20808 | 0 | 2647 | 39068 | 0 | 70062.0 | 131072.0 | 0.0 | 45782.0 | 64 | 0x7f1c3083cec0 | 0 | 4330318 | 2840 | 2840 | 0 | 3426749 | 2868 | 2868 | 0 | 3504767 | 2856 | 2856 | 0 | 3931420 | 2836 | 2836 | 0 | 3325380 | 2876 | 2876 | 0 | 4130117 | 2844 | 2844 | 0 | 3139565 | 2856 | 2856 | 0 | 4266411 | 2828 | 2828 | 0 | 3495466 | 2820 | 2820 | 0 | 4519191 | 2834 | 2834 | 0 | 3586841 | 2868 | 2868 | 0 | 3118187 | 2852 | 2852 | 0 | 3171777 | 2836 | 2836 | 0 | 4439257 | 2876 | 2876 | 0 | 4745545 | 2844 | 2844 | 0 | 3463541 | 2858 | 2858 | 0 | 3117032 | 2812 | 2812 | 0 | 3961551 | 2848 | 2848 | 0 | 4045052 | 2844 | 2844 | 0 | 3403891 | 2860 | 2860 | 0 | 3986132 | 2824 | 2824 | 0 | 3731800 | 2878 | 2878 | 0 | 4754579 | 2824 | 2824 | 0 | 4375906 | 2832 | 2832 | 0 | 4351714 | 2830 | 2830 | 0 | 2972415 | 2812 | 2812 | 0 | 3540266 | 2852 | 2852 | 0 | 3320714 | 2844 | 2844 | 0 | 4155841 | 2860 | 2860 | 0 | 3429068 | 2824 | 2824 | 0 | 3092763 | 2880 | 2880 | 0 | 3521856 | 2824 | 2824 | 64 | 0x7f2d2947cec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 29169 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 239.0 | 32768.0 | 4096 | 16384 | 302 | 40080 | 1933 | 0 | 56.0 | 9.0 | 0.0 | 200220.0 | 64 | 0x7f553b0b0ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131083.0 | 101033.0 | 45525.0 | 0.0 | 64 | 0x7effc4ae8ec0 | 0 | 188262 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f123191cec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 114564364.0 | 55936691.0 | 0.0 | 64 | 0x7f637f758ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 2023601.0 | 64 | 0x7fb1db9c4ec0 | 6275 | 0 | 4096 | 6249 | 0 | 4096 | 6241 | 0 | 4096 | 6246 | 0 | 4096 | 6240 | 0 | 4096 | 6242 | 0 | 4096 | 6254 | 0 | 4096 | 6230 | 0 | 4096 | 6233 | 0 | 4096 | 6277 | 0 | 4096 | 6254 | 0 | 4096 | 6243 | 0 | 4096 | 6252 | 0 | 4096 | 6241 | 0 | 4096 | 6244 | 0 | 4096 | 6254 | 0 | 4096 | 6241 | 0 | 4096 | 6238 | 0 | 4096 | 6274 | 0 | 4096 | 6283 | 0 | 4096 | 6229 | 0 | 4096 | 6242 | 0 | 4096 | 6236 | 0 | 4096 | 6229 | 0 | 4096 | 6228 | 0 | 4096 | 6243 | 0 | 4096 | 6238 | 0 | 4096 | 6275 | 0 | 4096 | 6283 | 0 | 4096 | 6228 | 0 | 4096 | 6243 | 0 | 4096 | 6238 | 0 | 4096 | 200174259950853 | 200174259967493 |