rocm-systems/tests/workloads/dispatch_2/MI100/pmc_perf.csv

1	Dispatch_ID	Kernel_Name	GPU_ID	Grid_Size	Workgroup_Size	LDS_Per_Workgroup	Scratch_Per_Workitem	Arch_VGPR	Accum_VGPR	SGPR	wave_size	obj	SQC_DCACHE_REQ_READ_2	SQC_DCACHE_REQ_READ_4	SQ_INSTS_VMEM_WR	SQ_INSTS_VMEM_RD	SQ_INSTS_VMEM	SQ_INSTS_SALU	SQ_INSTS_VSKIPPED	SQ_INSTS_SMEM	TCP_TOTAL_ATOMIC_WITH_RET_sum	TCP_TOTAL_ATOMIC_WITHOUT_RET_sum	TCP_TOTAL_WRITEBACK_INVALIDATES_sum	TCP_TOTAL_CACHE_ACCESSES_sum	TA_BUFFER_COALESCED_READ_CYCLES_sum	TA_BUFFER_COALESCED_WRITE_CYCLES_sum	SPI_RA_RES_STALL_CSN	SPI_RA_TMP_STALL_CSN	CPC_CPC_UTCL2IU_BUSY	CPC_CPC_UTCL2IU_IDLE	CPF_CMP_UTCL1_STALL_ON_TRANSLATION	TCC_READ_sum	TCC_WRITE_sum	TCC_ATOMIC_sum	TCC_WRITEBACK_sum	wave_size_1	obj_1	SQ_CYCLES	SQ_BUSY_CYCLES	SQ_BUSY_CU_CYCLES	SQ_WAVES	SQ_WAVE_CYCLES	SQC_TC_INST_REQ	SQC_TC_DATA_READ_REQ	SQC_TC_DATA_WRITE_REQ	GRBM_COUNT	GRBM_GUI_ACTIVE	TCP_GATE_EN1_sum	TCP_GATE_EN2_sum	TCP_TD_TCP_STALL_CYCLES_sum	TCP_TCR_TCP_STALL_CYCLES_sum	TA_TA_BUSY_sum	TA_BUFFER_WAVEFRONTS_sum	TD_TD_BUSY_sum	TD_TC_STALL_sum	SPI_CSN_WINDOW_VALID	SPI_CSN_BUSY	CPC_CPC_STAT_BUSY	CPC_CPC_STAT_IDLE	CPF_CPF_STAT_BUSY	CPF_CPF_STAT_STALL	TCC_CYCLE_sum	TCC_BUSY_sum	TCC_PROBE_sum	TCC_PROBE_ALL_sum	wave_size_2	obj_2	TCC_EA_RDREQ_IO_CREDIT_STALL[0]	TCC_EA_RDREQ_LEVEL[0]	TCC_EA_WRREQ[0]	TCC_EA_WRREQ_64B[0]	TCC_EA_RDREQ_IO_CREDIT_STALL[1]	TCC_EA_RDREQ_LEVEL[1]	TCC_EA_WRREQ[1]	TCC_EA_WRREQ_64B[1]	TCC_EA_RDREQ_IO_CREDIT_STALL[2]	TCC_EA_RDREQ_LEVEL[2]	TCC_EA_WRREQ[2]	TCC_EA_WRREQ_64B[2]	TCC_EA_RDREQ_IO_CREDIT_STALL[3]	TCC_EA_RDREQ_LEVEL[3]	TCC_EA_WRREQ[3]	TCC_EA_WRREQ_64B[3]	TCC_EA_RDREQ_IO_CREDIT_STALL[4]	TCC_EA_RDREQ_LEVEL[4]	TCC_EA_WRREQ[4]	TCC_EA_WRREQ_64B[4]	TCC_EA_RDREQ_IO_CREDIT_STALL[5]	TCC_EA_RDREQ_LEVEL[5]	TCC_EA_WRREQ[5]	TCC_EA_WRREQ_64B[5]	TCC_EA_RDREQ_IO_CREDIT_STALL[6]	TCC_EA_RDREQ_LEVEL[6]	TCC_EA_WRREQ[6]	TCC_EA_WRREQ_64B[6]	TCC_EA_RDREQ_IO_CREDIT_STALL[7]	TCC_EA_RDREQ_LEVEL[7]	TCC_EA_WRREQ[7]	TCC_EA_WRREQ_64B[7]	TCC_EA_RDREQ_IO_CREDIT_STALL[8]	TCC_EA_RDREQ_LEVEL[8]	TCC_EA_WRREQ[8]	TCC_EA_WRREQ_64B[8]	TCC_EA_RDREQ_IO_CREDIT_STALL[9]	TCC_EA_RDREQ_LEVEL[9]	TCC_EA_WRREQ[9]	TCC_EA_WRREQ_64B[9]	TCC_EA_RDREQ_IO_CREDIT_STALL[10]	TCC_EA_RDREQ_LEVEL[10]	TCC_EA_WRREQ[10]	TCC_EA_WRREQ_64B[10]	TCC_EA_RDREQ_IO_CREDIT_STALL[11]	TCC_EA_RDREQ_LEVEL[11]	TCC_EA_WRREQ[11]	TCC_EA_WRREQ_64B[11]	TCC_EA_RDREQ_IO_CREDIT_STALL[12]	TCC_EA_RDREQ_LEVEL[12]	TCC_EA_WRREQ[12]	TCC_EA_WRREQ_64B[12]	TCC_EA_RDREQ_IO_CREDIT_STALL[13]	TCC_EA_RDREQ_LEVEL[13]	TCC_EA_WRREQ[13]	TCC_EA_WRREQ_64B[13]	TCC_EA_RDREQ_IO_CREDIT_STALL[14]	TCC_EA_RDREQ_LEVEL[14]	TCC_EA_WRREQ[14]	TCC_EA_WRREQ_64B[14]	TCC_EA_RDREQ_IO_CREDIT_STALL[15]	TCC_EA_RDREQ_LEVEL[15]	TCC_EA_WRREQ[15]	TCC_EA_WRREQ_64B[15]	TCC_EA_RDREQ_IO_CREDIT_STALL[16]	TCC_EA_RDREQ_LEVEL[16]	TCC_EA_WRREQ[16]	TCC_EA_WRREQ_64B[16]	TCC_EA_RDREQ_IO_CREDIT_STALL[17]	TCC_EA_RDREQ_LEVEL[17]	TCC_EA_WRREQ[17]	TCC_EA_WRREQ_64B[17]	TCC_EA_RDREQ_IO_CREDIT_STALL[18]	TCC_EA_RDREQ_LEVEL[18]	TCC_EA_WRREQ[18]	TCC_EA_WRREQ_64B[18]	TCC_EA_RDREQ_IO_CREDIT_STALL[19]	TCC_EA_RDREQ_LEVEL[19]	TCC_EA_WRREQ[19]	TCC_EA_WRREQ_64B[19]	TCC_EA_RDREQ_IO_CREDIT_STALL[20]	TCC_EA_RDREQ_LEVEL[20]	TCC_EA_WRREQ[20]	TCC_EA_WRREQ_64B[20]	TCC_EA_RDREQ_IO_CREDIT_STALL[21]	TCC_EA_RDREQ_LEVEL[21]	TCC_EA_WRREQ[21]	TCC_EA_WRREQ_64B[21]	TCC_EA_RDREQ_IO_CREDIT_STALL[22]	TCC_EA_RDREQ_LEVEL[22]	TCC_EA_WRREQ[22]	TCC_EA_WRREQ_64B[22]	TCC_EA_RDREQ_IO_CREDIT_STALL[23]	TCC_EA_RDREQ_LEVEL[23]	TCC_EA_WRREQ[23]	TCC_EA_WRREQ_64B[23]	TCC_EA_RDREQ_IO_CREDIT_STALL[24]	TCC_EA_RDREQ_LEVEL[24]	TCC_EA_WRREQ[24]	TCC_EA_WRREQ_64B[24]	TCC_EA_RDREQ_IO_CREDIT_STALL[25]	TCC_EA_RDREQ_LEVEL[25]	TCC_EA_WRREQ[25]	TCC_EA_WRREQ_64B[25]	TCC_EA_RDREQ_IO_CREDIT_STALL[26]	TCC_EA_RDREQ_LEVEL[26]	TCC_EA_WRREQ[26]	TCC_EA_WRREQ_64B[26]	TCC_EA_RDREQ_IO_CREDIT_STALL[27]	TCC_EA_RDREQ_LEVEL[27]	TCC_EA_WRREQ[27]	TCC_EA_WRREQ_64B[27]	TCC_EA_RDREQ_IO_CREDIT_STALL[28]	TCC_EA_RDREQ_LEVEL[28]	TCC_EA_WRREQ[28]	TCC_EA_WRREQ_64B[28]	TCC_EA_RDREQ_IO_CREDIT_STALL[29]	TCC_EA_RDREQ_LEVEL[29]	TCC_EA_WRREQ[29]	TCC_EA_WRREQ_64B[29]	TCC_EA_RDREQ_IO_CREDIT_STALL[30]	TCC_EA_RDREQ_LEVEL[30]	TCC_EA_WRREQ[30]	TCC_EA_WRREQ_64B[30]	TCC_EA_RDREQ_IO_CREDIT_STALL[31]	TCC_EA_RDREQ_LEVEL[31]	TCC_EA_WRREQ[31]	TCC_EA_WRREQ_64B[31]	wave_size_3	obj_3	SQC_DCACHE_INPUT_VALID_READYB	SQC_DCACHE_ATOMIC	SQC_DCACHE_REQ_READ_8	SQC_DCACHE_REQ	SQC_DCACHE_HITS	SQC_DCACHE_MISSES	SQC_DCACHE_MISSES_DUPLICATE	SQC_DCACHE_REQ_READ_1	TCP_VOLATILE_sum	TCP_TOTAL_ACCESSES_sum	TCP_TOTAL_READ_sum	TCP_TOTAL_WRITE_sum	TA_BUFFER_ATOMIC_WAVEFRONTS_sum	TA_BUFFER_TOTAL_CYCLES_sum	TD_ATOMIC_WAVEFRONT_sum	TD_STORE_WAVEFRONT_sum	SPI_RA_REQ_NO_ALLOC	SPI_RA_REQ_NO_ALLOC_CSN	CPC_CPC_STAT_STALL	CPC_UTCL1_STALL_ON_TRANSLATION	CPF_CPF_STAT_IDLE	CPF_CPF_TCIU_IDLE	TCC_REQ_sum	TCC_STREAMING_REQ_sum	TCC_HIT_sum	TCC_MISS_sum	wave_size_4	obj_4	SQ_WAIT_INST_ANY	SQ_ACTIVE_INST_ANY	SQ_INSTS_VALU	SQ_ACTIVE_INST_VMEM	SQ_ACTIVE_INST_LDS	SQ_ACTIVE_INST_VALU	SQ_ACTIVE_INST_SCA	SQ_ACTIVE_INST_EXP_GDS	TCP_TCP_LATENCY_sum	TCP_TCC_READ_REQ_LATENCY_sum	TCP_TCC_WRITE_REQ_LATENCY_sum	TCP_TCC_READ_REQ_sum	TA_ADDR_STALLED_BY_TD_CYCLES_sum	TA_DATA_STALLED_BY_TC_CYCLES_sum	SPI_RA_SGPR_SIMD_FULL_CSN	SPI_RA_LDS_CU_FULL_CSN	CPC_ME1_DC0_SPI_BUSY	TCC_EA_WRREQ_STALL_sum	TCC_EA_WRREQ_IO_CREDIT_STALL_sum	TCC_EA_WRREQ_GMI_CREDIT_STALL_sum	TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum	wave_size_5	obj_5	SQ_INSTS_FLAT	SQ_INSTS_LDS	SQ_INSTS_GDS	SQ_INSTS_EXP_GDS	SQ_INSTS_BRANCH	SQ_INSTS_SENDMSG	SQ_INSTS	SQ_WAIT_ANY	TCP_UTCL1_TRANSLATION_MISS_sum	TCP_UTCL1_TRANSLATION_HIT_sum	TCP_UTCL1_PERMISSION_MISS_sum	TCP_UTCL1_REQUEST_sum	TA_ADDR_STALLED_BY_TC_CYCLES_sum	TA_TOTAL_WAVEFRONTS_sum	SPI_RA_WAVE_SIMD_FULL_CSN	SPI_RA_VGPR_SIMD_FULL_CSN	CPC_CPC_UTCL2IU_STALL	CPC_ME1_BUSY_FOR_PACKET_DECODE	TCC_EA_WRREQ_sum	TCC_EA_WRREQ_64B_sum	TCC_EA_WR_UNCACHED_32B_sum	TCC_EA_WRREQ_DRAM_sum	wave_size_6	obj_6	SQ_ACTIVE_INST_MISC	SQ_ACTIVE_INST_FLAT	SQ_INST_CYCLES_VMEM_WR	SQ_INST_CYCLES_VMEM_RD	SQ_INST_CYCLES_SMEM	SQ_INST_CYCLES_SALU	SQ_THREAD_CYCLES_VALU	SQ_IFETCH	TCP_TCC_WRITE_REQ_sum	TCP_TCC_ATOMIC_WITH_RET_REQ_sum	TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum	TCP_TCC_NC_READ_REQ_sum	TA_FLAT_WAVEFRONTS_sum	TA_FLAT_READ_WAVEFRONTS_sum	SPI_RA_BAR_CU_FULL_CSN	SPI_RA_TGLIM_CU_FULL_CSN	TCC_EA_RDREQ_sum	TCC_EA_RDREQ_32B_sum	TCC_EA_RD_UNCACHED_32B_sum	TCC_EA_RDREQ_DRAM_sum	wave_size_7	obj_7	SQ_LDS_BANK_CONFLICT	SQ_LDS_ADDR_CONFLICT	SQ_LDS_UNALIGNED_STALL	SQ_WAVES_EQ_64	SQ_WAVES_LT_64	SQ_WAVES_LT_48	SQ_WAVES_LT_32	SQ_WAVES_LT_16	TCP_TCC_NC_WRITE_REQ_sum	TCP_TCC_NC_ATOMIC_REQ_sum	TCP_TCC_UC_READ_REQ_sum	TCP_TCC_UC_WRITE_REQ_sum	TA_FLAT_WRITE_WAVEFRONTS_sum	TA_FLAT_ATOMIC_WAVEFRONTS_sum	SPI_RA_WVLIM_STALL_CSN	SPI_SWC_CSC_WR	TCC_EA_RDREQ_IO_CREDIT_STALL_sum	TCC_EA_RDREQ_GMI_CREDIT_STALL_sum	TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum	TCC_TAG_STALL_sum	wave_size_8	obj_8	TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]	TCC_EA_WRREQ_GMI_CREDIT_STALL[0]	TCC_EA_WRREQ_IO_CREDIT_STALL[0]	TCC_EA_WRREQ_LEVEL[0]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]	TCC_EA_WRREQ_GMI_CREDIT_STALL[1]	TCC_EA_WRREQ_IO_CREDIT_STALL[1]	TCC_EA_WRREQ_LEVEL[1]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]	TCC_EA_WRREQ_GMI_CREDIT_STALL[2]	TCC_EA_WRREQ_IO_CREDIT_STALL[2]	TCC_EA_WRREQ_LEVEL[2]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]	TCC_EA_WRREQ_GMI_CREDIT_STALL[3]	TCC_EA_WRREQ_IO_CREDIT_STALL[3]	TCC_EA_WRREQ_LEVEL[3]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]	TCC_EA_WRREQ_GMI_CREDIT_STALL[4]	TCC_EA_WRREQ_IO_CREDIT_STALL[4]	TCC_EA_WRREQ_LEVEL[4]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]	TCC_EA_WRREQ_GMI_CREDIT_STALL[5]	TCC_EA_WRREQ_IO_CREDIT_STALL[5]	TCC_EA_WRREQ_LEVEL[5]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]	TCC_EA_WRREQ_GMI_CREDIT_STALL[6]	TCC_EA_WRREQ_IO_CREDIT_STALL[6]	TCC_EA_WRREQ_LEVEL[6]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]	TCC_EA_WRREQ_GMI_CREDIT_STALL[7]	TCC_EA_WRREQ_IO_CREDIT_STALL[7]	TCC_EA_WRREQ_LEVEL[7]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]	TCC_EA_WRREQ_GMI_CREDIT_STALL[8]	TCC_EA_WRREQ_IO_CREDIT_STALL[8]	TCC_EA_WRREQ_LEVEL[8]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]	TCC_EA_WRREQ_GMI_CREDIT_STALL[9]	TCC_EA_WRREQ_IO_CREDIT_STALL[9]	TCC_EA_WRREQ_LEVEL[9]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]	TCC_EA_WRREQ_GMI_CREDIT_STALL[10]	TCC_EA_WRREQ_IO_CREDIT_STALL[10]	TCC_EA_WRREQ_LEVEL[10]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]	TCC_EA_WRREQ_GMI_CREDIT_STALL[11]	TCC_EA_WRREQ_IO_CREDIT_STALL[11]	TCC_EA_WRREQ_LEVEL[11]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]	TCC_EA_WRREQ_GMI_CREDIT_STALL[12]	TCC_EA_WRREQ_IO_CREDIT_STALL[12]	TCC_EA_WRREQ_LEVEL[12]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]	TCC_EA_WRREQ_GMI_CREDIT_STALL[13]	TCC_EA_WRREQ_IO_CREDIT_STALL[13]	TCC_EA_WRREQ_LEVEL[13]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]	TCC_EA_WRREQ_GMI_CREDIT_STALL[14]	TCC_EA_WRREQ_IO_CREDIT_STALL[14]	TCC_EA_WRREQ_LEVEL[14]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]	TCC_EA_WRREQ_GMI_CREDIT_STALL[15]	TCC_EA_WRREQ_IO_CREDIT_STALL[15]	TCC_EA_WRREQ_LEVEL[15]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]	TCC_EA_WRREQ_GMI_CREDIT_STALL[16]	TCC_EA_WRREQ_IO_CREDIT_STALL[16]	TCC_EA_WRREQ_LEVEL[16]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]	TCC_EA_WRREQ_GMI_CREDIT_STALL[17]	TCC_EA_WRREQ_IO_CREDIT_STALL[17]	TCC_EA_WRREQ_LEVEL[17]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]	TCC_EA_WRREQ_GMI_CREDIT_STALL[18]	TCC_EA_WRREQ_IO_CREDIT_STALL[18]	TCC_EA_WRREQ_LEVEL[18]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]	TCC_EA_WRREQ_GMI_CREDIT_STALL[19]	TCC_EA_WRREQ_IO_CREDIT_STALL[19]	TCC_EA_WRREQ_LEVEL[19]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]	TCC_EA_WRREQ_GMI_CREDIT_STALL[20]	TCC_EA_WRREQ_IO_CREDIT_STALL[20]	TCC_EA_WRREQ_LEVEL[20]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]	TCC_EA_WRREQ_GMI_CREDIT_STALL[21]	TCC_EA_WRREQ_IO_CREDIT_STALL[21]	TCC_EA_WRREQ_LEVEL[21]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]	TCC_EA_WRREQ_GMI_CREDIT_STALL[22]	TCC_EA_WRREQ_IO_CREDIT_STALL[22]	TCC_EA_WRREQ_LEVEL[22]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]	TCC_EA_WRREQ_GMI_CREDIT_STALL[23]	TCC_EA_WRREQ_IO_CREDIT_STALL[23]	TCC_EA_WRREQ_LEVEL[23]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]	TCC_EA_WRREQ_GMI_CREDIT_STALL[24]	TCC_EA_WRREQ_IO_CREDIT_STALL[24]	TCC_EA_WRREQ_LEVEL[24]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]	TCC_EA_WRREQ_GMI_CREDIT_STALL[25]	TCC_EA_WRREQ_IO_CREDIT_STALL[25]	TCC_EA_WRREQ_LEVEL[25]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]	TCC_EA_WRREQ_GMI_CREDIT_STALL[26]	TCC_EA_WRREQ_IO_CREDIT_STALL[26]	TCC_EA_WRREQ_LEVEL[26]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]	TCC_EA_WRREQ_GMI_CREDIT_STALL[27]	TCC_EA_WRREQ_IO_CREDIT_STALL[27]	TCC_EA_WRREQ_LEVEL[27]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]	TCC_EA_WRREQ_GMI_CREDIT_STALL[28]	TCC_EA_WRREQ_IO_CREDIT_STALL[28]	TCC_EA_WRREQ_LEVEL[28]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]	TCC_EA_WRREQ_GMI_CREDIT_STALL[29]	TCC_EA_WRREQ_IO_CREDIT_STALL[29]	TCC_EA_WRREQ_LEVEL[29]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]	TCC_EA_WRREQ_GMI_CREDIT_STALL[30]	TCC_EA_WRREQ_IO_CREDIT_STALL[30]	TCC_EA_WRREQ_LEVEL[30]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]	TCC_EA_WRREQ_GMI_CREDIT_STALL[31]	TCC_EA_WRREQ_IO_CREDIT_STALL[31]	TCC_EA_WRREQ_LEVEL[31]	wave_size_9	obj_9	TCC_EA_RDREQ[0]	TCC_EA_RDREQ_32B[0]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]	TCC_EA_RDREQ_GMI_CREDIT_STALL[0]	TCC_EA_RDREQ[1]	TCC_EA_RDREQ_32B[1]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]	TCC_EA_RDREQ_GMI_CREDIT_STALL[1]	TCC_EA_RDREQ[2]	TCC_EA_RDREQ_32B[2]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]	TCC_EA_RDREQ_GMI_CREDIT_STALL[2]	TCC_EA_RDREQ[3]	TCC_EA_RDREQ_32B[3]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]	TCC_EA_RDREQ_GMI_CREDIT_STALL[3]	TCC_EA_RDREQ[4]	TCC_EA_RDREQ_32B[4]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]	TCC_EA_RDREQ_GMI_CREDIT_STALL[4]	TCC_EA_RDREQ[5]	TCC_EA_RDREQ_32B[5]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]	TCC_EA_RDREQ_GMI_CREDIT_STALL[5]	TCC_EA_RDREQ[6]	TCC_EA_RDREQ_32B[6]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]	TCC_EA_RDREQ_GMI_CREDIT_STALL[6]	TCC_EA_RDREQ[7]	TCC_EA_RDREQ_32B[7]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]	TCC_EA_RDREQ_GMI_CREDIT_STALL[7]	TCC_EA_RDREQ[8]	TCC_EA_RDREQ_32B[8]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]	TCC_EA_RDREQ_GMI_CREDIT_STALL[8]	TCC_EA_RDREQ[9]	TCC_EA_RDREQ_32B[9]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]	TCC_EA_RDREQ_GMI_CREDIT_STALL[9]	TCC_EA_RDREQ[10]	TCC_EA_RDREQ_32B[10]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]	TCC_EA_RDREQ_GMI_CREDIT_STALL[10]	TCC_EA_RDREQ[11]	TCC_EA_RDREQ_32B[11]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]	TCC_EA_RDREQ_GMI_CREDIT_STALL[11]	TCC_EA_RDREQ[12]	TCC_EA_RDREQ_32B[12]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]	TCC_EA_RDREQ_GMI_CREDIT_STALL[12]	TCC_EA_RDREQ[13]	TCC_EA_RDREQ_32B[13]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]	TCC_EA_RDREQ_GMI_CREDIT_STALL[13]	TCC_EA_RDREQ[14]	TCC_EA_RDREQ_32B[14]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]	TCC_EA_RDREQ_GMI_CREDIT_STALL[14]	TCC_EA_RDREQ[15]	TCC_EA_RDREQ_32B[15]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]	TCC_EA_RDREQ_GMI_CREDIT_STALL[15]	TCC_EA_RDREQ[16]	TCC_EA_RDREQ_32B[16]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]	TCC_EA_RDREQ_GMI_CREDIT_STALL[16]	TCC_EA_RDREQ[17]	TCC_EA_RDREQ_32B[17]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]	TCC_EA_RDREQ_GMI_CREDIT_STALL[17]	TCC_EA_RDREQ[18]	TCC_EA_RDREQ_32B[18]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]	TCC_EA_RDREQ_GMI_CREDIT_STALL[18]	TCC_EA_RDREQ[19]	TCC_EA_RDREQ_32B[19]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]	TCC_EA_RDREQ_GMI_CREDIT_STALL[19]	TCC_EA_RDREQ[20]	TCC_EA_RDREQ_32B[20]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]	TCC_EA_RDREQ_GMI_CREDIT_STALL[20]	TCC_EA_RDREQ[21]	TCC_EA_RDREQ_32B[21]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]	TCC_EA_RDREQ_GMI_CREDIT_STALL[21]	TCC_EA_RDREQ[22]	TCC_EA_RDREQ_32B[22]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]	TCC_EA_RDREQ_GMI_CREDIT_STALL[22]	TCC_EA_RDREQ[23]	TCC_EA_RDREQ_32B[23]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]	TCC_EA_RDREQ_GMI_CREDIT_STALL[23]	TCC_EA_RDREQ[24]	TCC_EA_RDREQ_32B[24]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]	TCC_EA_RDREQ_GMI_CREDIT_STALL[24]	TCC_EA_RDREQ[25]	TCC_EA_RDREQ_32B[25]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]	TCC_EA_RDREQ_GMI_CREDIT_STALL[25]	TCC_EA_RDREQ[26]	TCC_EA_RDREQ_32B[26]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]	TCC_EA_RDREQ_GMI_CREDIT_STALL[26]	TCC_EA_RDREQ[27]	TCC_EA_RDREQ_32B[27]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]	TCC_EA_RDREQ_GMI_CREDIT_STALL[27]	TCC_EA_RDREQ[28]	TCC_EA_RDREQ_32B[28]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]	TCC_EA_RDREQ_GMI_CREDIT_STALL[28]	TCC_EA_RDREQ[29]	TCC_EA_RDREQ_32B[29]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]	TCC_EA_RDREQ_GMI_CREDIT_STALL[29]	TCC_EA_RDREQ[30]	TCC_EA_RDREQ_32B[30]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]	TCC_EA_RDREQ_GMI_CREDIT_STALL[30]	TCC_EA_RDREQ[31]	TCC_EA_RDREQ_32B[31]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]	TCC_EA_RDREQ_GMI_CREDIT_STALL[31]	wave_size_10	obj_10	SQ_ITEMS	SQ_LDS_MEM_VIOLATIONS	SQ_LDS_ATOMIC_RETURN	SQ_LDS_IDX_ACTIVE	SQ_WAVES_RESTORED	SQ_WAVES_SAVED	SQ_INSTS_SMEM_NORM	TCP_TCC_UC_ATOMIC_REQ_sum	TCP_TCC_CC_READ_REQ_sum	TCP_TCC_CC_WRITE_REQ_sum	TCP_TCC_CC_ATOMIC_REQ_sum	SPI_VWC_CSC_WR	SPI_RA_BULKY_CU_FULL_CSN	TCC_NORMAL_WRITEBACK_sum	TCC_ALL_TC_OP_WB_WRITEBACK_sum	TCC_NORMAL_EVICT_sum	TCC_ALL_TC_OP_INV_EVICT_sum	wave_size_11	obj_11	TCC_HIT[0]	TCC_MISS[0]	TCC_READ[0]	TCC_REQ[0]	TCC_HIT[1]	TCC_MISS[1]	TCC_READ[1]	TCC_REQ[1]	TCC_HIT[2]	TCC_MISS[2]	TCC_READ[2]	TCC_REQ[2]	TCC_HIT[3]	TCC_MISS[3]	TCC_READ[3]	TCC_REQ[3]	TCC_HIT[4]	TCC_MISS[4]	TCC_READ[4]	TCC_REQ[4]	TCC_HIT[5]	TCC_MISS[5]	TCC_READ[5]	TCC_REQ[5]	TCC_HIT[6]	TCC_MISS[6]	TCC_READ[6]	TCC_REQ[6]	TCC_HIT[7]	TCC_MISS[7]	TCC_READ[7]	TCC_REQ[7]	TCC_HIT[8]	TCC_MISS[8]	TCC_READ[8]	TCC_REQ[8]	TCC_HIT[9]	TCC_MISS[9]	TCC_READ[9]	TCC_REQ[9]	TCC_HIT[10]	TCC_MISS[10]	TCC_READ[10]	TCC_REQ[10]	TCC_HIT[11]	TCC_MISS[11]	TCC_READ[11]	TCC_REQ[11]	TCC_HIT[12]	TCC_MISS[12]	TCC_READ[12]	TCC_REQ[12]	TCC_HIT[13]	TCC_MISS[13]	TCC_READ[13]	TCC_REQ[13]	TCC_HIT[14]	TCC_MISS[14]	TCC_READ[14]	TCC_REQ[14]	TCC_HIT[15]	TCC_MISS[15]	TCC_READ[15]	TCC_REQ[15]	TCC_HIT[16]	TCC_MISS[16]	TCC_READ[16]	TCC_REQ[16]	TCC_HIT[17]	TCC_MISS[17]	TCC_READ[17]	TCC_REQ[17]	TCC_HIT[18]	TCC_MISS[18]	TCC_READ[18]	TCC_REQ[18]	TCC_HIT[19]	TCC_MISS[19]	TCC_READ[19]	TCC_REQ[19]	TCC_HIT[20]	TCC_MISS[20]	TCC_READ[20]	TCC_REQ[20]	TCC_HIT[21]	TCC_MISS[21]	TCC_READ[21]	TCC_REQ[21]	TCC_HIT[22]	TCC_MISS[22]	TCC_READ[22]	TCC_REQ[22]	TCC_HIT[23]	TCC_MISS[23]	TCC_READ[23]	TCC_REQ[23]	TCC_HIT[24]	TCC_MISS[24]	TCC_READ[24]	TCC_REQ[24]	TCC_HIT[25]	TCC_MISS[25]	TCC_READ[25]	TCC_REQ[25]	TCC_HIT[26]	TCC_MISS[26]	TCC_READ[26]	TCC_REQ[26]	TCC_HIT[27]	TCC_MISS[27]	TCC_READ[27]	TCC_REQ[27]	TCC_HIT[28]	TCC_MISS[28]	TCC_READ[28]	TCC_REQ[28]	TCC_HIT[29]	TCC_MISS[29]	TCC_READ[29]	TCC_REQ[29]	TCC_HIT[30]	TCC_MISS[30]	TCC_READ[30]	TCC_REQ[30]	TCC_HIT[31]	TCC_MISS[31]	TCC_READ[31]	TCC_REQ[31]	wave_size_12	obj_12	TCC_EA_ATOMIC_LEVEL_sum	wave_size_13	obj_13	SQC_TC_DATA_ATOMIC_REQ	SQC_TC_STALL	SQC_TC_REQ	SQC_DCACHE_REQ_READ_16	SQC_ICACHE_REQ	SQC_ICACHE_HITS	SQC_ICACHE_MISSES	SQC_ICACHE_MISSES_DUPLICATE	GRBM_SPI_BUSY	TCP_READ_TAGCONFLICT_STALL_CYCLES_sum	TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum	TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum	TCP_TA_TCP_STATE_READ_sum	TA_BUFFER_READ_WAVEFRONTS_sum	TA_BUFFER_WRITE_WAVEFRONTS_sum	TD_COALESCABLE_WAVEFRONT_sum	TD_LOAD_WAVEFRONT_sum	SPI_CSN_NUM_THREADGROUPS	SPI_CSN_WAVE	CPC_CPC_TCIU_BUSY	CPC_CPC_TCIU_IDLE	CPF_CPF_TCIU_BUSY	CPF_CPF_TCIU_STALL	TCC_NC_REQ_sum	TCC_UC_REQ_sum	TCC_CC_REQ_sum	TCC_RW_REQ_sum	wave_size_14	obj_14	TCC_RW_REQ[0]	TCC_TOO_MANY_EA_WRREQS_STALL[0]	TCC_WRITE[0]	TCC_RW_REQ[1]	TCC_TOO_MANY_EA_WRREQS_STALL[1]	TCC_WRITE[1]	TCC_RW_REQ[2]	TCC_TOO_MANY_EA_WRREQS_STALL[2]	TCC_WRITE[2]	TCC_RW_REQ[3]	TCC_TOO_MANY_EA_WRREQS_STALL[3]	TCC_WRITE[3]	TCC_RW_REQ[4]	TCC_TOO_MANY_EA_WRREQS_STALL[4]	TCC_WRITE[4]	TCC_RW_REQ[5]	TCC_TOO_MANY_EA_WRREQS_STALL[5]	TCC_WRITE[5]	TCC_RW_REQ[6]	TCC_TOO_MANY_EA_WRREQS_STALL[6]	TCC_WRITE[6]	TCC_RW_REQ[7]	TCC_TOO_MANY_EA_WRREQS_STALL[7]	TCC_WRITE[7]	TCC_RW_REQ[8]	TCC_TOO_MANY_EA_WRREQS_STALL[8]	TCC_WRITE[8]	TCC_RW_REQ[9]	TCC_TOO_MANY_EA_WRREQS_STALL[9]	TCC_WRITE[9]	TCC_RW_REQ[10]	TCC_TOO_MANY_EA_WRREQS_STALL[10]	TCC_WRITE[10]	TCC_RW_REQ[11]	TCC_TOO_MANY_EA_WRREQS_STALL[11]	TCC_WRITE[11]	TCC_RW_REQ[12]	TCC_TOO_MANY_EA_WRREQS_STALL[12]	TCC_WRITE[12]	TCC_RW_REQ[13]	TCC_TOO_MANY_EA_WRREQS_STALL[13]	TCC_WRITE[13]	TCC_RW_REQ[14]	TCC_TOO_MANY_EA_WRREQS_STALL[14]	TCC_WRITE[14]	TCC_RW_REQ[15]	TCC_TOO_MANY_EA_WRREQS_STALL[15]	TCC_WRITE[15]	TCC_RW_REQ[16]	TCC_TOO_MANY_EA_WRREQS_STALL[16]	TCC_WRITE[16]	TCC_RW_REQ[17]	TCC_TOO_MANY_EA_WRREQS_STALL[17]	TCC_WRITE[17]	TCC_RW_REQ[18]	TCC_TOO_MANY_EA_WRREQS_STALL[18]	TCC_WRITE[18]	TCC_RW_REQ[19]	TCC_TOO_MANY_EA_WRREQS_STALL[19]	TCC_WRITE[19]	TCC_RW_REQ[20]	TCC_TOO_MANY_EA_WRREQS_STALL[20]	TCC_WRITE[20]	TCC_RW_REQ[21]	TCC_TOO_MANY_EA_WRREQS_STALL[21]	TCC_WRITE[21]	TCC_RW_REQ[22]	TCC_TOO_MANY_EA_WRREQS_STALL[22]	TCC_WRITE[22]	TCC_RW_REQ[23]	TCC_TOO_MANY_EA_WRREQS_STALL[23]	TCC_WRITE[23]	TCC_RW_REQ[24]	TCC_TOO_MANY_EA_WRREQS_STALL[24]	TCC_WRITE[24]	TCC_RW_REQ[25]	TCC_TOO_MANY_EA_WRREQS_STALL[25]	TCC_WRITE[25]	TCC_RW_REQ[26]	TCC_TOO_MANY_EA_WRREQS_STALL[26]	TCC_WRITE[26]	TCC_RW_REQ[27]	TCC_TOO_MANY_EA_WRREQS_STALL[27]	TCC_WRITE[27]	TCC_RW_REQ[28]	TCC_TOO_MANY_EA_WRREQS_STALL[28]	TCC_WRITE[28]	TCC_RW_REQ[29]	TCC_TOO_MANY_EA_WRREQS_STALL[29]	TCC_WRITE[29]	TCC_RW_REQ[30]	TCC_TOO_MANY_EA_WRREQS_STALL[30]	TCC_WRITE[30]	TCC_RW_REQ[31]	TCC_TOO_MANY_EA_WRREQS_STALL[31]	TCC_WRITE[31]	wave_size_15	obj_15	TCP_TCC_RW_READ_REQ_sum	TCP_TCC_RW_WRITE_REQ_sum	TCP_TCC_RW_ATOMIC_REQ_sum	TCP_PENDING_STALL_CYCLES_sum	TCC_TOO_MANY_EA_WRREQS_STALL_sum	TCC_EA_ATOMIC_sum	TCC_EA_RDREQ_LEVEL_sum	TCC_EA_WRREQ_LEVEL_sum	wave_size_16	obj_16	TCC_ATOMIC[0]	TCC_CYCLE[0]	TCC_EA_ATOMIC[0]	TCC_EA_ATOMIC_LEVEL[0]	TCC_ATOMIC[1]	TCC_CYCLE[1]	TCC_EA_ATOMIC[1]	TCC_EA_ATOMIC_LEVEL[1]	TCC_ATOMIC[2]	TCC_CYCLE[2]	TCC_EA_ATOMIC[2]	TCC_EA_ATOMIC_LEVEL[2]	TCC_ATOMIC[3]	TCC_CYCLE[3]	TCC_EA_ATOMIC[3]	TCC_EA_ATOMIC_LEVEL[3]	TCC_ATOMIC[4]	TCC_CYCLE[4]	TCC_EA_ATOMIC[4]	TCC_EA_ATOMIC_LEVEL[4]	TCC_ATOMIC[5]	TCC_CYCLE[5]	TCC_EA_ATOMIC[5]	TCC_EA_ATOMIC_LEVEL[5]	TCC_ATOMIC[6]	TCC_CYCLE[6]	TCC_EA_ATOMIC[6]	TCC_EA_ATOMIC_LEVEL[6]	TCC_ATOMIC[7]	TCC_CYCLE[7]	TCC_EA_ATOMIC[7]	TCC_EA_ATOMIC_LEVEL[7]	TCC_ATOMIC[8]	TCC_CYCLE[8]	TCC_EA_ATOMIC[8]	TCC_EA_ATOMIC_LEVEL[8]	TCC_ATOMIC[9]	TCC_CYCLE[9]	TCC_EA_ATOMIC[9]	TCC_EA_ATOMIC_LEVEL[9]	TCC_ATOMIC[10]	TCC_CYCLE[10]	TCC_EA_ATOMIC[10]	TCC_EA_ATOMIC_LEVEL[10]	TCC_ATOMIC[11]	TCC_CYCLE[11]	TCC_EA_ATOMIC[11]	TCC_EA_ATOMIC_LEVEL[11]	TCC_ATOMIC[12]	TCC_CYCLE[12]	TCC_EA_ATOMIC[12]	TCC_EA_ATOMIC_LEVEL[12]	TCC_ATOMIC[13]	TCC_CYCLE[13]	TCC_EA_ATOMIC[13]	TCC_EA_ATOMIC_LEVEL[13]	TCC_ATOMIC[14]	TCC_CYCLE[14]	TCC_EA_ATOMIC[14]	TCC_EA_ATOMIC_LEVEL[14]	TCC_ATOMIC[15]	TCC_CYCLE[15]	TCC_EA_ATOMIC[15]	TCC_EA_ATOMIC_LEVEL[15]	TCC_ATOMIC[16]	TCC_CYCLE[16]	TCC_EA_ATOMIC[16]	TCC_EA_ATOMIC_LEVEL[16]	TCC_ATOMIC[17]	TCC_CYCLE[17]	TCC_EA_ATOMIC[17]	TCC_EA_ATOMIC_LEVEL[17]	TCC_ATOMIC[18]	TCC_CYCLE[18]	TCC_EA_ATOMIC[18]	TCC_EA_ATOMIC_LEVEL[18]	TCC_ATOMIC[19]	TCC_CYCLE[19]	TCC_EA_ATOMIC[19]	TCC_EA_ATOMIC_LEVEL[19]	TCC_ATOMIC[20]	TCC_CYCLE[20]	TCC_EA_ATOMIC[20]	TCC_EA_ATOMIC_LEVEL[20]	TCC_ATOMIC[21]	TCC_CYCLE[21]	TCC_EA_ATOMIC[21]	TCC_EA_ATOMIC_LEVEL[21]	TCC_ATOMIC[22]	TCC_CYCLE[22]	TCC_EA_ATOMIC[22]	TCC_EA_ATOMIC_LEVEL[22]	TCC_ATOMIC[23]	TCC_CYCLE[23]	TCC_EA_ATOMIC[23]	TCC_EA_ATOMIC_LEVEL[23]	TCC_ATOMIC[24]	TCC_CYCLE[24]	TCC_EA_ATOMIC[24]	TCC_EA_ATOMIC_LEVEL[24]	TCC_ATOMIC[25]	TCC_CYCLE[25]	TCC_EA_ATOMIC[25]	TCC_EA_ATOMIC_LEVEL[25]	TCC_ATOMIC[26]	TCC_CYCLE[26]	TCC_EA_ATOMIC[26]	TCC_EA_ATOMIC_LEVEL[26]	TCC_ATOMIC[27]	TCC_CYCLE[27]	TCC_EA_ATOMIC[27]	TCC_EA_ATOMIC_LEVEL[27]	TCC_ATOMIC[28]	TCC_CYCLE[28]	TCC_EA_ATOMIC[28]	TCC_EA_ATOMIC_LEVEL[28]	TCC_ATOMIC[29]	TCC_CYCLE[29]	TCC_EA_ATOMIC[29]	TCC_EA_ATOMIC_LEVEL[29]	TCC_ATOMIC[30]	TCC_CYCLE[30]	TCC_EA_ATOMIC[30]	TCC_EA_ATOMIC_LEVEL[30]	TCC_ATOMIC[31]	TCC_CYCLE[31]	TCC_EA_ATOMIC[31]	TCC_EA_ATOMIC_LEVEL[31]	Start_Timestamp	End_Timestamp
2	1	vecCopy(double*, double*, double*, int, int)	2	1048576	256	0	0	8	8	16	64	0x7f1d8c15ee80	32768	0	16384	16384	32768	49152	0	65536	0.0	0.0	120.0	524288.0	0.0	0.0	0	0	913	38058	0	131120.0	131072.0	0.0	86666.0	64	0x7f7344748e80	316552	217305	3164765	16384	22802950	0	48	0	39568	39568	3548909.0	2953421.0	6333.0	1143383.0	1920174.0	0.0	2943829.0	2632025.0	314839	225366	39568	0	39568	0	1266176.0	803963.0	0.0	0.0	64	0x7fe9644bce80	0	5222995	2682	2682	0	3392075	2734	2734	0	3756922	2702	2702	0	4271945	2722	2722	0	4163839	2680	2680	0	3733566	2727	2727	0	3781930	2710	2710	0	5226561	2722	2722	0	2922815	2693	2693	0	5120054	2696	2696	0	3169518	2720	2720	0	4835632	2728	2728	0	3195743	2684	2684	0	3687677	2688	2688	0	4623675	2708	2708	0	3783480	2708	2708	0	3381916	2659	2659	0	3821247	2732	2732	0	3517105	2698	2698	0	4983992	2726	2726	0	3292152	2680	2680	0	4115210	2741	2741	0	4127291	2668	2668	0	3662849	2726	2726	0	2898666	2664	2664	0	4099866	2725	2725	0	3485860	2744	2744	0	3590091	2708	2708	0	4445905	2692	2692	0	4517792	2709	2709	0	4868968	2720	2720	0	3131958	2712	2712	64	0x7f7dee84ee80	113445	0	0	65536	64048	48	1440	32768	2097152.0	2097152.0	1048576.0	1048576.0	0.0	0.0	0.0	16384.0	12112	28496	7653	588	0	37317	262192.0	0.0	47.0	262145.0	64	0x7f7054060e80	232735	360448	163840	0	0	180224	114688	0	72780046.0	215262519.0	82111247.0	131072.0	0.0	561955.0	0	0	23176	85311.0	0.0	0.0	85311.0	64	0x7f5a5a6bae80	32768	0	0	0	16384	16384	393216	22039488	0.0	524288.0	0.0	524288.0	740876.0	32768.0	0	0	0	11985	86563.0	86563.0	0.0	86563.0	64	0x7f1b2c53ce80	32768	32768	16384	16384	65536	49152	11534336	65536	131072.0	0.0	0.0	0.0	32768.0	16384.0	0	0	131073.0	0.0	0.0	131072.0	64	0x7fa720d58e80	0	0	0	16384	0	0	0	0	0.0	0.0	0.0	0.0	16384.0	0.0	0	81920	0.0	0.0	26071.0	99136.0	64	0x7f05f0f54e80	1817	0	0	1465710	1225	0	0	1347096	1601	0	0	1328810	1773	0	0	1448741	1292	0	0	1334314	463	0	0	1284833	3676	0	0	1675403	803	0	0	1376596	1023	0	0	1331919	1355	0	0	1364751	2601	0	0	1568619	625	0	0	1363566	1373	0	0	1409928	782	0	0	1305101	812	0	0	1209792	726	0	0	1261650	1443	0	0	1398748	1779	0	0	1496283	357	0	0	1118800	5005	0	0	1754840	308	0	0	1124542	1979	0	0	1459692	698	0	0	1380954	1104	0	0	1343945	453	0	0	1245581	1294	0	0	1424018	2422	0	0	1495284	4014	0	0	1668796	2033	0	0	1439203	907	0	0	1295852	722	0	0	1296558	2365	0	0	1511383	64	0x7f6069bb2e80	4096	0	2290	0	4096	0	880	0	4096	0	789	0	4096	0	427	0	4097	0	4003	0	4096	0	573	0	4096	0	1851	0	4096	0	535	0	4096	0	5726	0	4096	0	1981	0	4096	0	4482	0	4096	0	183	0	4096	0	1570	0	4096	0	3036	0	4096	0	3194	0	4096	0	1713	0	4096	0	2348	0	4096	0	3235	0	4096	0	2424	0	4096	0	2633	0	4096	0	503	0	4096	0	3667	0	4096	0	4279	0	4096	0	1518	0	4096	0	1682	0	4096	0	889	0	4096	0	589	0	4096	0	862	0	4096	0	1454	0	4096	0	435	0	4096	0	2009	0	4096	0	111	0	64	0x7fb601d70e80	1048576	0	0	0	0	0	131072	0.0	0.0	0.0	0.0	16384	0	86737.0	0.0	131110.0	0.0	64	0x7f4c9939ae80	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	47	8193	4144	8240	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	0	8192	4096	8192	64	0x7fe83f9ece80	0.0	64	0x7f95399eae80	0	0	48	0	65536	65536	0	0	28472	0.0	0.0	0.0	32768.0	0.0	0.0	0.0	32768.0	4096	16384	435	38030	1753	0	48.0	0.0	0.0	262144.0	64	0x7f6a01166e80	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	8192	0	4096	64	0x7fc0cfb26e80	131072.0	131072.0	0.0	2689705.0	0.0	0.0	120492860.0	44290488.0	64	0x7f1f59a4ae80	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	0	38643	0	0	4855077119856	4855077138416