Jose Santos
34 KiB
34 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | SQ_INSTS_SMEM_NORM | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | wave_size_1 | obj_1 | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_EA_RDREQ_IO_CREDIT_STALL_sum | TCC_EA_RDREQ_GMI_CREDIT_STALL_sum | TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum | TCC_TAG_STALL_sum | wave_size_2 | obj_2 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_3 | obj_3 | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | SQC_DCACHE_REQ_READ_1 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_4 | obj_4 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_BUSY_CU_CYCLES | SQ_WAVES | SQ_WAVE_CYCLES | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | SQC_TC_DATA_WRITE_REQ | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_5 | obj_5 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | SQ_INSTS_VSKIPPED | SQ_INSTS_SMEM | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_6 | obj_6 | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_7 | obj_7 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_8 | obj_8 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_9 | obj_9 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_10 | obj_10 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | wave_size_11 | obj_11 | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | wave_size_12 | obj_12 | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | SQ_INSTS | SQ_WAIT_ANY | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_13 | obj_13 | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | SQC_ICACHE_MISSES_DUPLICATE | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_COALESCABLE_WAVEFRONT_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_14 | obj_14 | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | TCC_EA_RDREQ_DRAM_sum | wave_size_15 | obj_15 | TCC_EA_ATOMIC_LEVEL_sum | wave_size_16 | obj_16 | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_INSTS_VALU | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_WRREQ_IO_CREDIT_STALL_sum | TCC_EA_WRREQ_GMI_CREDIT_STALL_sum | TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f1369e54e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86752.0 | 44320.0 | 131112.0 | 0.0 | 64 | 0x7fb001d70e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 53123.0 | 125386.0 | 64 | 0x7f43663a2e80 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8474 | 4378 | 8474 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 141 | 8243 | 4288 | 8384 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7fbd30a0ce80 | 192310 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 10387 | 26771 | 9523 | 588 | 0 | 46024 | 262585.0 | 0.0 | 188.0 | 262397.0 | 64 | 0x7f4e1158ce80 | 379664 | 233147 | 3419858 | 16384 | 25128778 | 144 | 48 | 0 | 47457 | 47457 | 3849837.0 | 2972887.0 | 6301.0 | 1071170.0 | 2049781.0 | 0.0 | 2963578.0 | 2652276.0 | 378015 | 243104 | 47457 | 0 | 47457 | 0 | 1518624.0 | 956888.0 | 0.0 | 0.0 | 64 | 0x7f4974dd0e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 913 | 46666 | 0 | 131599.0 | 131072.0 | 0.0 | 131104.0 | 64 | 0x7f8095b7ce80 | 0 | 3458465 | 4096 | 4096 | 0 | 3596944 | 4096 | 4096 | 0 | 3356940 | 4096 | 4096 | 0 | 2698136 | 4096 | 4096 | 0 | 3211531 | 4096 | 4096 | 0 | 3835409 | 4096 | 4096 | 0 | 3562298 | 4096 | 4096 | 0 | 3232232 | 4096 | 4096 | 0 | 3142732 | 4096 | 4096 | 0 | 3636386 | 4096 | 4096 | 0 | 3358455 | 4096 | 4096 | 0 | 4084308 | 4096 | 4096 | 0 | 3062261 | 4096 | 4096 | 0 | 3172526 | 4096 | 4096 | 0 | 2897495 | 4096 | 4096 | 0 | 4424544 | 4096 | 4096 | 0 | 3949002 | 4096 | 4096 | 0 | 3654703 | 4096 | 4096 | 0 | 5447813 | 4096 | 4096 | 0 | 2898469 | 4096 | 4096 | 0 | 2758466 | 4096 | 4096 | 0 | 3173645 | 4096 | 4096 | 0 | 4219020 | 4096 | 4096 | 0 | 2822780 | 4096 | 4096 | 0 | 5035639 | 4096 | 4096 | 0 | 4265617 | 4096 | 4096 | 0 | 3186161 | 4096 | 4096 | 0 | 3312968 | 4096 | 4096 | 0 | 3142199 | 4096 | 4096 | 0 | 3385785 | 4096 | 4096 | 0 | 3175696 | 4096 | 4096 | 0 | 2748078 | 4096 | 4096 | 64 | 0x7f64fa0bee80 | 2977 | 0 | 0 | 1893884 | 2266 | 0 | 0 | 1865393 | 1807 | 0 | 0 | 1788639 | 3240 | 0 | 0 | 1947171 | 1273 | 0 | 0 | 1737761 | 1807 | 0 | 0 | 1832511 | 1954 | 0 | 0 | 1763370 | 2107 | 0 | 0 | 1815652 | 3307 | 0 | 0 | 1915600 | 1996 | 0 | 0 | 1760692 | 3131 | 0 | 0 | 2033649 | 2107 | 0 | 0 | 1887080 | 2856 | 0 | 0 | 1914993 | 4922 | 0 | 0 | 2140688 | 1387 | 0 | 0 | 1748066 | 1720 | 0 | 0 | 1860206 | 3741 | 0 | 0 | 2020934 | 3384 | 0 | 0 | 2026634 | 2959 | 0 | 0 | 1905666 | 1321 | 0 | 0 | 1829288 | 2154 | 0 | 0 | 1817207 | 1147 | 0 | 0 | 1816686 | 2712 | 0 | 0 | 1908112 | 2649 | 0 | 0 | 1920005 | 2869 | 0 | 0 | 1971481 | 1434 | 0 | 0 | 1744504 | 2787 | 0 | 0 | 1945911 | 2590 | 0 | 0 | 1908140 | 3141 | 0 | 0 | 1871841 | 4183 | 0 | 0 | 2011960 | 2231 | 0 | 0 | 1911941 | 1384 | 0 | 0 | 1702142 | 64 | 0x7f086e252e80 | 4096 | 0 | 420 | 0 | 4096 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 86 | 0 | 4096 | 0 | 930 | 0 | 4096 | 0 | 84 | 0 | 4096 | 0 | 247 | 0 | 4096 | 0 | 461 | 0 | 4096 | 0 | 261 | 0 | 4096 | 0 | 148 | 0 | 4096 | 0 | 2853 | 0 | 4192 | 0 | 319 | 0 | 4096 | 0 | 663 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 850 | 0 | 4096 | 0 | 138 | 0 | 4096 | 0 | 455 | 0 | 4096 | 0 | 1259 | 0 | 4096 | 0 | 451 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 633 | 0 | 4096 | 0 | 1421 | 0 | 4096 | 0 | 485 | 0 | 4096 | 0 | 1524 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 6258 | 0 | 4096 | 0 | 29 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 24 | 0 | 4216 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 6196 | 0 | 64 | 0x7fa693c18e80 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 0 | 48431 | 0 | 0 | 64 | 0x7fcf06eb0e80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8336 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7fcd02664e80 | 131072.0 | 131072.0 | 0.0 | 2553272.0 | 0.0 | 0.0 | 121032895.0 | 59454997.0 | 64 | 0x7f6a92878e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22758365 | 960.0 | 513920.0 | 0.0 | 524288.0 | 963936.0 | 32768.0 | 0 | 0 | 0 | 16346 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7f69134aae80 | 0 | 0 | 192 | 0 | 65536 | 64403 | 48 | 1358 | 31839 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 512 | 47563 | 1710 | 0 | 48.0 | 264.0 | 0.0 | 262288.0 | 64 | 0x7f7248872e80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131390.0 | 0.0 | 628.0 | 131389.0 | 64 | 0x7f67818d8e80 | 0.0 | 64 | 0x7f4b8f87ce80 | 3266999 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 66453567.0 | 176144131.0 | 71223999.0 | 131072.0 | 0.0 | 612071.0 | 0 | 0 | 27207 | 76711.0 | 0.0 | 0.0 | 76711.0 | 5001214170932 | 5001214195252 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f1369e54e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86522.0 | 0.0 | 131110.0 | 0.0 | 64 | 0x7fb001d70e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 66264.0 | 134657.0 | 64 | 0x7f43663a2e80 | 0 | 8241 | 4145 | 8241 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8479 | 4383 | 8479 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7fbd30a0ce80 | 260695 | 0 | 0 | 65536 | 62560 | 96 | 2880 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 11281 | 27665 | 26031 | 6654 | 0 | 43218 | 262967.0 | 0.0 | 94.0 | 262873.0 | 64 | 0x7f4e1158ce80 | 405472 | 262812 | 3840713 | 16384 | 28909628 | 0 | 96 | 0 | 50683 | 50683 | 4231211.0 | 3357380.0 | 3628.0 | 1149404.0 | 2483741.0 | 0.0 | 3339336.0 | 3025576.0 | 405464 | 272259 | 50683 | 0 | 50683 | 1223 | 1621856.0 | 905933.0 | 1.0 | 0.0 | 64 | 0x7f4974dd0e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 5985 | 39333 | 0 | 131467.0 | 131072.0 | 0.0 | 87114.0 | 64 | 0x7f8095b7ce80 | 0 | 4386621 | 2704 | 2704 | 0 | 3872330 | 2742 | 2742 | 0 | 2630156 | 2654 | 2654 | 0 | 3659502 | 2702 | 2702 | 0 | 4571051 | 2682 | 2682 | 0 | 3510262 | 2730 | 2730 | 0 | 2732582 | 2660 | 2660 | 0 | 3500400 | 2700 | 2700 | 0 | 4196641 | 2706 | 2706 | 0 | 4602934 | 2684 | 2684 | 0 | 2985099 | 2684 | 2684 | 0 | 4221166 | 2726 | 2726 | 0 | 4169815 | 2690 | 2690 | 0 | 4510373 | 2700 | 2700 | 0 | 4049935 | 2671 | 2671 | 0 | 4029886 | 2686 | 2686 | 0 | 4213335 | 2704 | 2704 | 0 | 4855681 | 2728 | 2728 | 0 | 4024281 | 2676 | 2676 | 0 | 4890602 | 2720 | 2720 | 0 | 4183997 | 2694 | 2694 | 0 | 4757899 | 2739 | 2739 | 0 | 3713986 | 2672 | 2672 | 0 | 4297660 | 2686 | 2686 | 0 | 4244720 | 2681 | 2681 | 0 | 4713123 | 2701 | 2701 | 0 | 3550606 | 2714 | 2714 | 0 | 4074294 | 2668 | 2668 | 0 | 3497905 | 2730 | 2730 | 0 | 3940702 | 2713 | 2713 | 0 | 3352998 | 2712 | 2712 | 0 | 3790822 | 2692 | 2692 | 64 | 0x7f64fa0bee80 | 3623 | 0 | 0 | 1635879 | 3170 | 0 | 0 | 1591333 | 2225 | 0 | 0 | 1494171 | 1841 | 0 | 0 | 1500004 | 823 | 0 | 0 | 1295875 | 1381 | 0 | 0 | 1322167 | 1510 | 0 | 0 | 1392307 | 1333 | 0 | 0 | 1439221 | 2505 | 0 | 0 | 1520762 | 938 | 0 | 0 | 1254304 | 3031 | 0 | 0 | 1612924 | 1242 | 0 | 0 | 1437230 | 1782 | 0 | 0 | 1447815 | 943 | 0 | 0 | 1344463 | 3517 | 0 | 0 | 1688526 | 2133 | 0 | 0 | 1511158 | 2062 | 0 | 0 | 1491148 | 502 | 0 | 0 | 1273380 | 1383 | 0 | 0 | 1443130 | 4516 | 0 | 0 | 1676786 | 792 | 0 | 0 | 1298135 | 1370 | 0 | 0 | 1396676 | 3874 | 0 | 0 | 1761453 | 6787 | 0 | 0 | 1841019 | 3597 | 0 | 0 | 1636761 | 405 | 0 | 0 | 1178429 | 4628 | 0 | 0 | 1774340 | 965 | 0 | 0 | 1317507 | 862 | 0 | 0 | 1339081 | 813 | 0 | 0 | 1252918 | 415 | 0 | 0 | 1289190 | 1903 | 0 | 0 | 1500807 | 64 | 0x7f086e252e80 | 4096 | 0 | 1254 | 0 | 4096 | 0 | 1512 | 0 | 4096 | 0 | 584 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 2345 | 0 | 4096 | 0 | 1034 | 0 | 4096 | 0 | 892 | 0 | 4096 | 0 | 252 | 0 | 4096 | 0 | 6179 | 0 | 4096 | 0 | 564 | 0 | 4096 | 0 | 3911 | 0 | 4192 | 0 | 1563 | 0 | 4096 | 0 | 698 | 0 | 4096 | 0 | 518 | 0 | 4096 | 0 | 5162 | 0 | 4096 | 0 | 465 | 0 | 4097 | 0 | 1988 | 0 | 4099 | 0 | 1566 | 0 | 4096 | 0 | 1052 | 0 | 4098 | 0 | 732 | 0 | 4096 | 0 | 395 | 0 | 4096 | 0 | 3464 | 0 | 4096 | 0 | 692 | 0 | 4096 | 0 | 5172 | 0 | 4096 | 0 | 4966 | 0 | 4096 | 0 | 553 | 0 | 4096 | 0 | 3894 | 0 | 4096 | 0 | 374 | 0 | 4096 | 0 | 1732 | 0 | 4216 | 0 | 2632 | 0 | 4096 | 0 | 3907 | 0 | 4097 | 0 | 390 | 0 | 64 | 0x7fa693c18e80 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 0 | 42747 | 0 | 0 | 64 | 0x7fcf06eb0e80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7fcd02664e80 | 131072.0 | 131072.0 | 0.0 | 2600047.0 | 0.0 | 0.0 | 129412593.0 | 46099922.0 | 64 | 0x7f6a92878e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22308742 | 960.0 | 513954.0 | 0.0 | 524288.0 | 929300.0 | 32768.0 | 0 | 0 | 0 | 13930 | 86426.0 | 86426.0 | 0.0 | 86426.0 | 64 | 0x7f69134aae80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 30657 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 508 | 42002 | 1757 | 0 | 48.0 | 270.0 | 0.0 | 262144.0 | 64 | 0x7f7248872e80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131320.0 | 0.0 | 494.0 | 131319.0 | 64 | 0x7f67818d8e80 | 0.0 | 64 | 0x7f4b8f87ce80 | 1793242 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 71131992.0 | 203038134.0 | 82119550.0 | 131072.0 | 0.0 | 651067.0 | 0 | 0 | 25919 | 72579.0 | 0.0 | 0.0 | 72579.0 | 5001214215892 | 5001214234612 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f1369e54e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86492.0 | 0.0 | 131112.0 | 0.0 | 64 | 0x7fb001d70e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 55286.0 | 120083.0 | 64 | 0x7f43663a2e80 | 0 | 8241 | 4145 | 8241 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8478 | 4382 | 8478 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7fbd30a0ce80 | 190990 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 13775 | 30159 | 8525 | 3221 | 0 | 40898 | 262444.0 | 0.0 | 47.0 | 262397.0 | 64 | 0x7f4e1158ce80 | 341968 | 229476 | 3353472 | 16384 | 24571564 | 0 | 48 | 0 | 42745 | 42745 | 3731404.0 | 2961750.0 | 6402.0 | 1104630.0 | 2008441.0 | 0.0 | 2953089.0 | 2642345.0 | 341960 | 239057 | 42745 | 0 | 42745 | 0 | 1367840.0 | 796191.0 | 0.0 | 0.0 | 64 | 0x7f4974dd0e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 2844 | 40563 | 0 | 131475.0 | 131072.0 | 0.0 | 87479.0 | 64 | 0x7f8095b7ce80 | 0 | 3574717 | 2735 | 2735 | 0 | 3801244 | 2744 | 2744 | 0 | 3183869 | 2698 | 2698 | 0 | 2959063 | 2688 | 2688 | 0 | 3999854 | 2717 | 2717 | 0 | 3877181 | 2734 | 2734 | 0 | 3244463 | 2706 | 2706 | 0 | 3240221 | 2674 | 2674 | 0 | 3752264 | 2712 | 2712 | 0 | 3584724 | 2692 | 2692 | 0 | 2942235 | 2710 | 2710 | 0 | 4353380 | 2699 | 2699 | 0 | 3076935 | 2700 | 2700 | 0 | 3720191 | 2724 | 2724 | 0 | 2692388 | 2692 | 2692 | 0 | 2744313 | 2680 | 2680 | 0 | 4135409 | 2726 | 2726 | 0 | 5268393 | 2728 | 2728 | 0 | 3075641 | 2694 | 2694 | 0 | 2873251 | 2696 | 2696 | 0 | 4246301 | 2708 | 2708 | 0 | 3213044 | 2766 | 2766 | 0 | 3053450 | 2714 | 2714 | 0 | 2527617 | 2692 | 2692 | 0 | 5154146 | 2699 | 2699 | 0 | 4354224 | 2714 | 2714 | 0 | 2923686 | 2756 | 2756 | 0 | 2700284 | 2664 | 2664 | 0 | 3529823 | 2744 | 2744 | 0 | 3797295 | 2725 | 2725 | 0 | 3813228 | 2716 | 2716 | 0 | 4004464 | 2688 | 2688 | 64 | 0x7f64fa0bee80 | 2423 | 0 | 0 | 1469344 | 2830 | 0 | 0 | 1546214 | 1881 | 0 | 0 | 1476112 | 3447 | 0 | 0 | 1550833 | 1996 | 0 | 0 | 1480463 | 1840 | 0 | 0 | 1460147 | 1315 | 0 | 0 | 1401347 | 3333 | 0 | 0 | 1604315 | 1629 | 0 | 0 | 1436090 | 1798 | 0 | 0 | 1472413 | 2054 | 0 | 0 | 1459519 | 3359 | 0 | 0 | 1621607 | 1140 | 0 | 0 | 1373662 | 1723 | 0 | 0 | 1446224 | 1476 | 0 | 0 | 1464032 | 6699 | 0 | 0 | 1858329 | 1888 | 0 | 0 | 1396245 | 1027 | 0 | 0 | 1336357 | 3907 | 0 | 0 | 1640875 | 3728 | 0 | 0 | 1651029 | 1472 | 0 | 0 | 1408627 | 2281 | 0 | 0 | 1495401 | 3082 | 0 | 0 | 1553438 | 5586 | 0 | 0 | 1748276 | 1798 | 0 | 0 | 1485039 | 984 | 0 | 0 | 1363400 | 3431 | 0 | 0 | 1601744 | 5455 | 0 | 0 | 1715735 | 2868 | 0 | 0 | 1587124 | 4586 | 0 | 0 | 1708634 | 2509 | 0 | 0 | 1578848 | 2431 | 0 | 0 | 1518814 | 64 | 0x7f086e252e80 | 4096 | 0 | 3803 | 0 | 4096 | 0 | 304 | 0 | 4096 | 0 | 2591 | 0 | 4096 | 0 | 2699 | 0 | 4096 | 0 | 3105 | 0 | 4096 | 0 | 1916 | 0 | 4096 | 0 | 116 | 0 | 4096 | 0 | 519 | 0 | 4096 | 0 | 770 | 0 | 4096 | 0 | 1900 | 0 | 4096 | 0 | 1636 | 0 | 4192 | 0 | 557 | 0 | 4096 | 0 | 2414 | 0 | 4096 | 0 | 1074 | 0 | 4096 | 0 | 667 | 0 | 4096 | 0 | 402 | 0 | 4097 | 0 | 1561 | 0 | 4099 | 0 | 1939 | 0 | 4096 | 0 | 2225 | 0 | 4098 | 0 | 2009 | 0 | 4096 | 0 | 1241 | 0 | 4096 | 0 | 1320 | 0 | 4096 | 0 | 2060 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 542 | 0 | 4096 | 0 | 519 | 0 | 4096 | 0 | 568 | 0 | 4096 | 0 | 24 | 0 | 4096 | 0 | 520 | 0 | 4216 | 0 | 5690 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 2617 | 0 | 64 | 0x7fa693c18e80 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 0 | 42391 | 0 | 0 | 64 | 0x7fcf06eb0e80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7fcd02664e80 | 131072.0 | 131072.0 | 0.0 | 2570333.0 | 0.0 | 0.0 | 125055350.0 | 45136488.0 | 64 | 0x7f6a92878e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22672222 | 960.0 | 513973.0 | 0.0 | 524288.0 | 954765.0 | 32768.0 | 0 | 0 | 0 | 14461 | 86322.0 | 86322.0 | 0.0 | 86322.0 | 64 | 0x7f69134aae80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 30943 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 432 | 41306 | 2011 | 0 | 48.0 | 270.0 | 0.0 | 262144.0 | 64 | 0x7f7248872e80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131360.0 | 0.0 | 574.0 | 131359.0 | 64 | 0x7f67818d8e80 | 0.0 | 64 | 0x7f4b8f87ce80 | 1583330 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 71315474.0 | 190847653.0 | 76854372.0 | 131072.0 | 0.0 | 638913.0 | 0 | 0 | 25710 | 51943.0 | 0.0 | 0.0 | 51943.0 | 5001214296052 | 5001214314932 |