David Yat Sin
aa2f98e6f9
Updating ROCr code to match new handshake protocol with CP FW for asynchronous scratch reclaim. Increase previous limits when scratch reclaim feature is available.
155 рядки
6.1 KiB
C
155 рядки
6.1 KiB
C
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef AMD_HSA_QUEUE_H
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#define AMD_HSA_QUEUE_H
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#include "amd_hsa_common.h"
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#include "hsa.h"
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// AMD Queue Properties.
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typedef uint32_t amd_queue_properties32_t;
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enum amd_queue_properties_t {
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER, 0, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_IS_PTR64, 1, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS, 2, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_ENABLE_PROFILING, 3, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE, 4, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_RESERVED1, 5, 27)
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};
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// AMD Queue.
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#define AMD_QUEUE_ALIGN_BYTES 64
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#define AMD_QUEUE_ALIGN __ALIGNED__(AMD_QUEUE_ALIGN_BYTES)
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// AMD Queue Capabilities.
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typedef uint32_t amd_queue_capabilities32_t;
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enum amd_queue_capabilities_t {
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/* This version of CP FW supports dual-scratch and async-reclaim */
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_CAPS_CP_ASYNC_RECLAIM, 0, 1),
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/*
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* This version of ROCr supports async-reclaim and CP FW may access the
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* V2 fields.
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*/
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_CAPS_SW_ASYNC_RECLAIM, 1, 1),
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};
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/* This is the original amd_queue_t structure. The definition is only kept
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* for reference purposes. This structure should not be used. */
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typedef struct AMD_QUEUE_ALIGN amd_queue_s {
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hsa_queue_t hsa_queue;
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uint32_t caps;
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uint32_t reserved1[3];
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volatile uint64_t write_dispatch_id;
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uint32_t group_segment_aperture_base_hi;
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uint32_t private_segment_aperture_base_hi;
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uint32_t max_cu_id;
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uint32_t max_wave_id;
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volatile uint64_t max_legacy_doorbell_dispatch_id_plus_1;
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volatile uint32_t legacy_doorbell_lock;
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uint32_t reserved2[9];
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volatile uint64_t read_dispatch_id;
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uint32_t read_dispatch_id_field_base_byte_offset;
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uint32_t compute_tmpring_size;
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uint32_t scratch_resource_descriptor[4];
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uint64_t scratch_backing_memory_location;
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uint64_t scratch_backing_memory_byte_size;
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uint32_t scratch_wave64_lane_byte_size;
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amd_queue_properties32_t queue_properties;
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uint32_t reserved3[2];
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hsa_signal_t queue_inactive_signal;
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uint32_t reserved4[14];
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} amd_queue_t;
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/*
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* AMD_QUEUE Version 2
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* amd_queue_v2_t is backwards compatible with amd_queue_t structure and can
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* be used with previous versions of CP FW. The added fields tagged as V2 are
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* ignored when running previous versions of CP FW.
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* CP FW will not try to access elements beyond the original 64-bytes
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* (sizeof(amd_queue_t)) unless the AMD_QUEUE_CAPS_SW_ASYNC_RECLAIM bit is set.
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*/
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#define MAX_NUM_XCC 128
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typedef struct scratch_last_used_index_xcc_s {
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volatile uint64_t main;
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volatile uint64_t alt;
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} scratch_last_used_index_xcc_t;
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typedef struct AMD_QUEUE_ALIGN amd_queue_v2_s {
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hsa_queue_t hsa_queue;
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uint32_t caps;
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uint32_t reserved1[3];
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volatile uint64_t write_dispatch_id;
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uint32_t group_segment_aperture_base_hi;
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uint32_t private_segment_aperture_base_hi;
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uint32_t max_cu_id;
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uint32_t max_wave_id;
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volatile uint64_t max_legacy_doorbell_dispatch_id_plus_1;
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volatile uint32_t legacy_doorbell_lock;
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uint32_t reserved2[9];
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volatile uint64_t read_dispatch_id;
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uint32_t read_dispatch_id_field_base_byte_offset;
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uint32_t compute_tmpring_size;
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uint32_t scratch_resource_descriptor[4];
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uint64_t scratch_backing_memory_location;
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uint32_t reserved3[2];
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uint32_t scratch_wave64_lane_byte_size;
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amd_queue_properties32_t queue_properties;
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volatile uint64_t scratch_max_use_index; /* V2 */
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hsa_signal_t queue_inactive_signal;
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volatile uint64_t alt_scratch_max_use_index; /* V2 */
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uint32_t alt_scratch_resource_descriptor[4]; /* V2 */
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uint64_t alt_scratch_backing_memory_location; /* V2 */
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uint32_t alt_scratch_dispatch_limit_x; /* V2 */
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uint32_t alt_scratch_dispatch_limit_y; /* V2 */
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uint32_t alt_scratch_dispatch_limit_z; /* V2 */
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uint32_t alt_scratch_wave64_lane_byte_size; /* V2 */
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uint32_t alt_compute_tmpring_size; /* V2 */
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uint32_t reserved5;
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scratch_last_used_index_xcc_t scratch_last_used_index[MAX_NUM_XCC];
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} amd_queue_v2_t;
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#endif // AMD_HSA_QUEUE_H
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