David Yat Sin
08626b6cf9
This avoids conflicts in case application is loading another copy of
addrlib.
Change-Id: Ifb4a10270c867366d5eed0a8c015257b415189a5
Signed-off-by: Chris Freehill <cfreehil@amd.com>
[ROCm/ROCR-Runtime commit: f1a13b6d87]
524 строки
19 KiB
C++
524 строки
19 KiB
C++
/*
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************************************************************************************************************************
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*
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* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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***********************************************************************************************************************/
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/**
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************************************************************************************************************************
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* @file gfx11addrlib.h
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* @brief Contains the Gfx11Lib class definition.
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************************************************************************************************************************
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*/
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#ifndef __GFX11_ADDR_LIB_H__
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#define __GFX11_ADDR_LIB_H__
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#include "addrlib2.h"
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#include "coord.h"
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#include "gfx11SwizzlePattern.h"
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namespace rocr {
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namespace Addr
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{
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namespace V2
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{
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/**
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************************************************************************************************************************
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* @brief GFX11 specific settings structure.
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************************************************************************************************************************
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*/
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struct Gfx11ChipSettings
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{
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struct
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{
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UINT_32 isGfx1150 : 1;
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UINT_32 isGfx1103 : 1;
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UINT_32 reserved1 : 30;
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// Misc configuration bits
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UINT_32 reserved2 : 32;
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};
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};
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/**
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************************************************************************************************************************
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* @brief GFX11 data surface type.
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************************************************************************************************************************
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*/
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enum Gfx11DataType
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{
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Gfx11DataColor,
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Gfx11DataDepthStencil,
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};
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const UINT_32 Gfx11LinearSwModeMask = (1u << ADDR_SW_LINEAR);
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const UINT_32 Gfx11Blk256BSwModeMask = (1u << ADDR_SW_256B_D);
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const UINT_32 Gfx11Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) |
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(1u << ADDR_SW_4KB_D) |
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(1u << ADDR_SW_4KB_S_X) |
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(1u << ADDR_SW_4KB_D_X);
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const UINT_32 Gfx11Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) |
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(1u << ADDR_SW_64KB_D) |
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(1u << ADDR_SW_64KB_S_T) |
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(1u << ADDR_SW_64KB_D_T) |
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(1u << ADDR_SW_64KB_Z_X) |
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(1u << ADDR_SW_64KB_S_X) |
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(1u << ADDR_SW_64KB_D_X) |
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(1u << ADDR_SW_64KB_R_X);
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const UINT_32 Gfx11Blk256KBSwModeMask = (1u << ADDR_SW_256KB_Z_X) |
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(1u << ADDR_SW_256KB_S_X) |
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(1u << ADDR_SW_256KB_D_X) |
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(1u << ADDR_SW_256KB_R_X);
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const UINT_32 Gfx11ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
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(1u << ADDR_SW_256KB_Z_X);
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const UINT_32 Gfx11StandardSwModeMask = (1u << ADDR_SW_4KB_S) |
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(1u << ADDR_SW_64KB_S) |
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(1u << ADDR_SW_64KB_S_T) |
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(1u << ADDR_SW_4KB_S_X) |
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(1u << ADDR_SW_64KB_S_X) |
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(1u << ADDR_SW_256KB_S_X);
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const UINT_32 Gfx11DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
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(1u << ADDR_SW_4KB_D) |
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(1u << ADDR_SW_64KB_D) |
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(1u << ADDR_SW_64KB_D_T) |
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(1u << ADDR_SW_4KB_D_X) |
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(1u << ADDR_SW_64KB_D_X) |
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(1u << ADDR_SW_256KB_D_X);
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const UINT_32 Gfx11RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) |
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(1u << ADDR_SW_256KB_R_X);
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const UINT_32 Gfx11XSwModeMask = (1u << ADDR_SW_4KB_S_X) |
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(1u << ADDR_SW_4KB_D_X) |
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(1u << ADDR_SW_64KB_Z_X) |
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(1u << ADDR_SW_64KB_S_X) |
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(1u << ADDR_SW_64KB_D_X) |
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(1u << ADDR_SW_64KB_R_X) |
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Gfx11Blk256KBSwModeMask;
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const UINT_32 Gfx11TSwModeMask = (1u << ADDR_SW_64KB_S_T) |
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(1u << ADDR_SW_64KB_D_T);
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const UINT_32 Gfx11XorSwModeMask = Gfx11XSwModeMask |
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Gfx11TSwModeMask;
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const UINT_32 Gfx11Rsrc1dSwModeMask = (1u << ADDR_SW_LINEAR) |
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(1u << ADDR_SW_64KB_R_X) |
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(1u << ADDR_SW_64KB_Z_X) ;
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const UINT_32 Gfx11Rsrc2dSwModeMask = Gfx11LinearSwModeMask |
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Gfx11DisplaySwModeMask |
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Gfx11ZSwModeMask |
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Gfx11RenderSwModeMask;
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const UINT_32 Gfx11Rsrc3dSwModeMask = Gfx11LinearSwModeMask |
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Gfx11StandardSwModeMask |
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Gfx11ZSwModeMask |
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Gfx11RenderSwModeMask |
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(1u << ADDR_SW_64KB_D_X) |
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(1u << ADDR_SW_256KB_D_X);
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const UINT_32 Gfx11Rsrc2dPrtSwModeMask =
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(Gfx11Blk4KBSwModeMask | Gfx11Blk64KBSwModeMask) & ~Gfx11XSwModeMask & Gfx11Rsrc2dSwModeMask;
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const UINT_32 Gfx11Rsrc3dPrtSwModeMask =
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(Gfx11Blk4KBSwModeMask | Gfx11Blk64KBSwModeMask) & ~Gfx11XSwModeMask & Gfx11Rsrc3dSwModeMask;
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const UINT_32 Gfx11Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
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(1u << ADDR_SW_64KB_R_X);
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const UINT_32 Gfx11Rsrc3dThin256KBSwModeMask = (1u << ADDR_SW_256KB_Z_X) |
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(1u << ADDR_SW_256KB_R_X);
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const UINT_32 Gfx11Rsrc3dThinSwModeMask = Gfx11Rsrc3dThin64KBSwModeMask | Gfx11Rsrc3dThin256KBSwModeMask;
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const UINT_32 Gfx11Rsrc3dThickSwModeMask = Gfx11Rsrc3dSwModeMask & ~(Gfx11Rsrc3dThinSwModeMask | Gfx11LinearSwModeMask);
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const UINT_32 Gfx11Rsrc3dThick4KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk4KBSwModeMask;
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const UINT_32 Gfx11Rsrc3dThick64KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk64KBSwModeMask;
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const UINT_32 Gfx11Rsrc3dThick256KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk256KBSwModeMask;
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const UINT_32 Gfx11MsaaSwModeMask = Gfx11ZSwModeMask |
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Gfx11RenderSwModeMask;
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const UINT_32 Dcn32SwModeMask = (1u << ADDR_SW_LINEAR) |
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(1u << ADDR_SW_64KB_D) |
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(1u << ADDR_SW_64KB_D_T) |
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(1u << ADDR_SW_64KB_D_X) |
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(1u << ADDR_SW_64KB_R_X) |
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(1u << ADDR_SW_256KB_D_X) |
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(1u << ADDR_SW_256KB_R_X);
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const UINT_32 Size256K = 262144u;
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const UINT_32 Log2Size256K = 18u;
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/**
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************************************************************************************************************************
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* @brief This class is the GFX11 specific address library
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* function set.
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************************************************************************************************************************
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*/
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class Gfx11Lib : public Lib
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{
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public:
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/// Creates Gfx11Lib object
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static Addr::Lib* CreateObj(const Client* pClient)
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{
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VOID* pMem = Object::ClientAlloc(sizeof(Gfx11Lib), pClient);
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return (pMem != NULL) ? new (pMem) Gfx11Lib(pClient) : NULL;
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}
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protected:
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Gfx11Lib(const Client* pClient);
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virtual ~Gfx11Lib();
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virtual BOOL_32 HwlIsStandardSwizzle(
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode) const
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{
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return m_swizzleModeTable[swizzleMode].isStd;
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}
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virtual BOOL_32 HwlIsDisplaySwizzle(
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode) const
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{
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return m_swizzleModeTable[swizzleMode].isDisp;
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}
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virtual BOOL_32 HwlIsThin(
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode) const
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{
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return ((IsTex1d(resourceType) == TRUE) ||
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(IsTex2d(resourceType) == TRUE) ||
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((IsTex3d(resourceType) == TRUE) &&
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(m_swizzleModeTable[swizzleMode].isStd == FALSE) &&
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(m_swizzleModeTable[swizzleMode].isDisp == FALSE)));
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}
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virtual BOOL_32 HwlIsThick(
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode) const
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{
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return ((IsTex3d(resourceType) == TRUE) &&
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(m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp));
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}
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virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
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const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
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const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
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ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
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const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
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ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
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virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
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const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
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ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
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virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord(
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const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn);
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virtual VOID HwlComputeDccAddrFromCoord(
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const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
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virtual UINT_32 HwlGetEquationIndex(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
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virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
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{
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*ppEquationTable = m_equationTable;
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return m_numEquations;
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}
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virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
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const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
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ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
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const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
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ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
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const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
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ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView(
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const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
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ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
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const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
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ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes(
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const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
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ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlGetAllowedBlockSet(
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ADDR2_SWMODE_SET allowedSwModeSet,
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AddrResourceType rsrcType,
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ADDR2_BLOCK_SET* pAllowedBlockSet) const;
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virtual ADDR_E_RETURNCODE HwlGetAllowedSwSet(
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ADDR2_SWMODE_SET allowedSwModeSet,
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ADDR2_SWTYPE_SET* pAllowedSwSet) const;
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virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
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virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
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virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
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const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
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virtual UINT_32 HwlComputeMaxBaseAlignments() const;
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virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
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virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn);
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virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
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private:
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// Initialize equation table
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VOID InitEquationTable();
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ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
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ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
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ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled(
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const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
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ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled(
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const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
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UINT_32 ComputeOffsetFromSwizzlePattern(
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const UINT_64* pPattern,
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UINT_32 numBits,
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UINT_32 x,
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UINT_32 y,
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UINT_32 z,
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UINT_32 s) const;
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UINT_32 ComputeOffsetFromEquation(
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const ADDR_EQUATION* pEq,
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UINT_32 x,
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UINT_32 y,
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UINT_32 z) const;
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ADDR_E_RETURNCODE ComputeStereoInfo(
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const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
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UINT_32* pAlignY,
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UINT_32* pRightXor) const;
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static void GetMipSize(
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UINT_32 mip0Width,
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UINT_32 mip0Height,
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UINT_32 mip0Depth,
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UINT_32 mipId,
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UINT_32* pMipWidth,
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UINT_32* pMipHeight,
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UINT_32* pMipDepth = NULL)
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{
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*pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId);
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*pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId);
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if (pMipDepth != NULL)
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{
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*pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId);
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}
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}
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const ADDR_SW_PATINFO* GetSwizzlePatternInfo(
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AddrSwizzleMode swizzleMode,
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AddrResourceType resourceType,
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UINT_32 log2Elem,
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UINT_32 numFrag) const;
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VOID GetSwizzlePatternFromPatternInfo(
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const ADDR_SW_PATINFO* pPatInfo,
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ADDR_BIT_SETTING (&pSwizzle)[20]) const
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{
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memcpy(pSwizzle,
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GFX11_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx],
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sizeof(GFX11_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx]));
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memcpy(&pSwizzle[8],
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GFX11_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx],
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sizeof(GFX11_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx]));
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memcpy(&pSwizzle[12],
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GFX11_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx],
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sizeof(GFX11_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx]));
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memcpy(&pSwizzle[16],
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GFX11_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx],
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sizeof(GFX11_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx]));
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}
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VOID ConvertSwizzlePatternToEquation(
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UINT_32 elemLog2,
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AddrResourceType rsrcType,
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AddrSwizzleMode swMode,
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const ADDR_SW_PATINFO* pPatInfo,
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ADDR_EQUATION* pEquation) const;
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static INT_32 GetMetaElementSizeLog2(Gfx11DataType dataType);
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static INT_32 GetMetaCacheSizeLog2(Gfx11DataType dataType);
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void GetBlk256SizeLog2(
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode,
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UINT_32 elemLog2,
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UINT_32 numSamplesLog2,
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Dim3d* pBlock) const;
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void GetCompressedBlockSizeLog2(
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Gfx11DataType dataType,
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode,
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UINT_32 elemLog2,
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UINT_32 numSamplesLog2,
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Dim3d* pBlock) const;
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INT_32 GetMetaOverlapLog2(
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Gfx11DataType dataType,
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode,
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UINT_32 elemLog2,
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UINT_32 numSamplesLog2) const;
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INT_32 Get3DMetaOverlapLog2(
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode,
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UINT_32 elemLog2) const;
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UINT_32 GetMetaBlkSize(
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Gfx11DataType dataType,
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AddrResourceType resourceType,
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AddrSwizzleMode swizzleMode,
|
|
UINT_32 elemLog2,
|
|
UINT_32 numSamplesLog2,
|
|
BOOL_32 pipeAlign,
|
|
Dim3d* pBlock) const;
|
|
|
|
INT_32 GetPipeRotateAmount(
|
|
AddrResourceType resourceType,
|
|
AddrSwizzleMode swizzleMode) const;
|
|
|
|
INT_32 GetEffectiveNumPipes() const
|
|
{
|
|
return ((m_numSaLog2 + 1) >= m_pipesLog2) ? m_pipesLog2 : m_numSaLog2 + 1;
|
|
}
|
|
|
|
BOOL_32 IsRbAligned(
|
|
AddrResourceType resourceType,
|
|
AddrSwizzleMode swizzleMode) const
|
|
{
|
|
const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode);
|
|
const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode);
|
|
const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode);
|
|
|
|
return (IsTex2d(resourceType) && (isRtopt || isZ)) ||
|
|
(IsTex3d(resourceType) && isDisplay);
|
|
|
|
}
|
|
|
|
UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const;
|
|
|
|
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
|
|
|
|
UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const;
|
|
|
|
BOOL_32 IsInMipTail(
|
|
Dim3d mipTailDim,
|
|
UINT_32 maxNumMipsInTail,
|
|
UINT_32 mipWidth,
|
|
UINT_32 mipHeight,
|
|
UINT_32 numMipsToTheEnd) const
|
|
{
|
|
BOOL_32 inTail = ((mipWidth <= mipTailDim.w) &&
|
|
(mipHeight <= mipTailDim.h) &&
|
|
(numMipsToTheEnd <= maxNumMipsInTail));
|
|
|
|
return inTail;
|
|
}
|
|
|
|
UINT_32 GetBankXorBits(UINT_32 blockBits) const
|
|
{
|
|
return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ?
|
|
Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0;
|
|
}
|
|
|
|
BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
|
|
BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
|
|
|
|
BOOL_32 IsBlock256kb(AddrSwizzleMode swizzleMode) const { return IsBlockVariable(swizzleMode); }
|
|
|
|
// TODO: figure out if there is any Column bits on GFX11...
|
|
static const UINT_32 ColumnBits = 2;
|
|
static const UINT_32 BankBits = 4;
|
|
static const UINT_32 UnalignedDccType = 3;
|
|
|
|
static const Dim3d Block256_3d[MaxNumOfBpp];
|
|
static const Dim3d Block256K_Log2_3d[MaxNumOfBpp];
|
|
static const Dim3d Block64K_Log2_3d[MaxNumOfBpp];
|
|
static const Dim3d Block4K_Log2_3d[MaxNumOfBpp];
|
|
|
|
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
|
|
|
|
// Number of packers log2
|
|
UINT_32 m_numPkrLog2;
|
|
// Number of shader array log2
|
|
UINT_32 m_numSaLog2;
|
|
|
|
Gfx11ChipSettings m_settings;
|
|
|
|
UINT_32 m_colorBaseIndex;
|
|
UINT_32 m_htileBaseIndex;
|
|
UINT_32 m_dccBaseIndex;
|
|
};
|
|
|
|
} // V2
|
|
} // Addr
|
|
} // namespace rocr
|
|
#endif
|
|
|